Abstract: A page table entry management method and apparatus provide the Microkernel System with the capability to program the memory management unit on the PowerPC family of processors. The PowerPC processors define a limited set of page table entries (PTEs) to maintain virtual to physical mappings. The page table entry management method and apparatus solves the problem of a limited number of PTEs by segment aliasing when two or more user processes share a segment of memory. The segments are aliased rather than duplicating the PTES. This significantly reduces the number of PTEs. In addition, the method provides for caching existing PTEs when the system actually runs out of PTEs. A cache of recently discarded PTEs provides a fast fault resolution when a recently used page is accessed again.
Type:
Grant
Filed:
May 22, 1997
Date of Patent:
October 23, 2001
Assignee:
International Business Machines Corporation
Inventors:
Dennis Frank Ackerman, Himanshu Harshadrai Desai, Ram Kishor Gupta, Ravi Rengarajan Strinivasan