Abstract: A regulating digital power supply in which an error detector compares a reference signal voltage with an unknown loop signal voltage and upon being strobed the error detector outputs a signal depending upon the relative magnitude of the two input signals. This output signal controls the direction of count of an up/down counter that counts clock pulses. At appropriate intervals as controlled by the clock, the contents of the up/down counter are transferred to a down counter upon a command signal which also sets a flip-flop. When the down counter reaches zero and overflows it emits a signal that resets the flip-flop, the output thereof being a pulsewidth modulated regulated power supply. The flip-flop also controls a switch to a power source that is rectified and filtered and then fed back to the error detector comparator, thereby completing the loop.