Abstract: A power integrated circuit including a substrate of semiconductor material having a first conductivity type on which is formed a first epitaxial layer of the same conductivity type. In a first portion of the first epitaxial layer are formed first and second diffused regions having respectively first and second conductivity type. The first and the second diffused regions are isolated from a power stage included partially in a second portion of the first epitaxial layer by an annular region having the second conductivity type. Over the first epitaxial layer is formed a second epitaxial layer having the first conductivity type in which are extended the first and the second diffused regions to permit forming a control circuitry for the power stage.

Abstract: Zener diode with high stability in time and low noise for integrated circuits and provided in an epitaxial pocket insulated from the rest of a type N epitaxial layer grown on a substrate of type P semiconductor material.In said pocket are included a type N+ cathode region and a type P anode region enclosing it.The cathode region has a peripheral part surrounding a central part extending in the anode region less deeply than the peripheral part.

Abstract: A method, and associated circuit, which can prevent the latch-down phenomenon in transistors which are protected from going out of their SOAs.By supplementing the first protection circuit (against moving out of the SOA) with a second protection circuit which can drive the control terminal of the transistor such that when, upon the voltage across the main conduction path of the transistor being increased, the value of the current flowing through said path would tend, due to the first protection, to drop below a predetermined lower limit, that value can be kept approximately constant and unaffected by the load as seen from the output terminal of the transistor; the transistor will at all events supply the load with some current up to the acceptable limit VMAX by the transistor.