Abstract: The contact probe arrangement includes a stack of perforated plates (1, 1a) through which extend a plurality contact probes. The stack of perforated plates consists of two kinds of plates. The first kind forms the lowermost plates (1a). They have circular or square holes permitting a vertical placing of the contact probes onto the contact pads (4) of the device (5) to be tested. The plates (1) of the second kind have oblong, rectangular, square, circular, elliptical or trapezoidal holes (3). With respect to the stacked plates of the second kind, alternate ones are offset against the two other adjacent plates which are aligned relative to each other, in such a manner that each contact probe is surrounded by part of the lower edge of the upper of two adjacent perforated plates, and part of the upper edge of the lower of two adjacent perforated plates. If axial stress is applied, the contact probe can thus not buckle any farther than to a part of the perforation wall limiting its maximum buckling.

Abstract: A process for reducing edge curl in green sheets in which the sheets are first placed in a chamber at about 95% relative humidity for a period of about 2 weeks at room temperature. In this part of the process, the sheets absorb water which causes the internal stresses in the green sheet to relax. Thereafter, the sheets are dried by placing them in a chamber at about 35% relative humidity for a period of about 1 week at room temperature. In this period, the absorbed water evaporates and the green sheets become firm with less edge curl than they exhibited prior to the treatment.

Abstract: A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more of less binary ones or zeros.

Abstract: Disclosed is an improved bit selection circuit for a RAM, in particular one employing CTS (complementary transistor switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto a bit select circuit, each of the bit select circuits being connected to an output of the second level decoder, a bit up-level clamp circuit connected to each of the bit select circuits of each pair of bit lines, each of the bit select circuits including a first circuit for increasing the speed of selection of the selected pair of lines, the bit up-level clamp circuit cooperating with the bit select circuit of the selected pair of bit lines for positively limiting the upper potential level of the selected pair of bit lines, and each of the bit select circuits including a second circuit for increasing the speed of deselection of the selected pair of bit lines.

Abstract: A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

Abstract: An attenuator useful in measuring low level leakage currents is disclosed. The attenuator includes a plurality of current dividers coupled in cascade. Each current divider includes an input and two outputs between which the current entering the input is divided. The current exiting the last divider is significantly attenuated from that entering the attenuator. The attenuator output is coupled to the device under test and to one input of a differential amplifier. A known current is input to the differential amplifier and part is directed to the attenuator input and the other part to a current measuring device. The difference between the known current input to the differential amplifier and that measured is the current input to the attenuator. In the steady state, the current input to the differential amplifier from the current attenuator is about zero.

Abstract: A tester of circuit devices is disclosed which uses commercially available component parts but is capable of high performance testing of hierarchical memory cards requiring data pulses of variable pulse widths at high repetition rates. The tester includes two memories connected to respective shift registers which in turn, feed a multiplexer. The memories handle test timing patterns for respective halves of the basic clock test cycle and are interleaved in operation along with the shift registers. Two opposite-phased outputs of the multiplexer are applied through respective programmable delay networks and pulse generators to the set and reset inputs of a trigger circuit. The trigger circuit provides test data to a dedicated input pin of the device under test.

Abstract: A heat sink is disclosed for cooling a module having a plurality of chip sites thereon. The heat sink includes a frame member which is made of a material having a coefficient of thermal expansion which is substantially that of the substrate to which it is bonded. The frame has a plurality of fins disposed around the perimeter and a support surface disposed inside the perimeter fins. An insert member made of a high thermal conductivity material rests on the support surface. The insert member has a plurality of fins disposed on one side thereof and a plurality of projections on the other side. Forced air flowing around the fins provides a mechanism for rapidly removing heat therefrom. Each of the projections is disposed above a chip site and extends almost into contact with the upper surface of a chip mounted on the module substrate. A thermal paste is used to transfer heat directly from the chip to the insert member hence a mechanism is provided for rapidly removing heat developed in each chip of the module.

Abstract: A thermal tester for measuring the efficiency of a heat transfer device for cooling semiconductor chips is disclosed having a positioning means operable to position the heat transfer device in thermal contact with the chip. The positioning means is adjustable in at least 5 degrees of freedom. Temperature sensors are provided to sense the temperature of the chip, the chip support substrate and the positioning means adjacent the heat transfer device. Means is provided to dispose the chip and heat transfer device in a vacuum. Control means is also provided to adjust the temperature of the chip unitl it is the same as the substrate to thereby assure heat transfer occurs only from the chip to the positioning means by way of the heat transfer device. When this thermal balance is achieved the thermal resistance of the heat transfer device can be calculated.

Abstract: A circuit and method for generating a read complete signal for a high speed densely packaged monolithic memory is disclosed. The memory is designed to utilize an externally generated address valid signal which indicates that the address to the memory is valid. The receipt of the address valid signal sets a set/reset latch and starts the memory. The addressed memory cells are sensed. When at least one memory cell has data at its output below a threshold, the data are said to be unstable and the set/reset latch is then conditioned to be reset. When the data sensed by all the sensing circuits are stable, a signal is sent to the set/reset latch to cause it to be reset. The resetting of the set/reset latch causes an output thereof to change state. This state change comprises the read complete signal which is used to determine the read cycle time of the memory and may also be used in diagnostic tests of the memory.

Abstract: A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation.The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

Abstract: A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

Abstract: The buckling beam probe contactor assembly comprises a number of square test probe arrays each containing a plurality of buckling beams in the form of continuous wires extending from the probe tips to a remote test apparatus. The buckling beams pass through an adjustable beam carrier block and through a number of guide plates which are kept in predetermined distances along the buckling beams by means of thin stabilizing rods arranged at the corners of the test probe array. The guide plates are inserted into grid-like frames which allow the arrangement of a plurality of test probe arrays close to each other wherein each array may contain test probes over its full area except for the locations occupied by the thin stabilizing rods.

Abstract: A method and apparatus for aligning a ceramic substrate provided with two small alignment crosses formed at the same time as the metallic pattern and located on both sides of a symmetry axis, said substrate being disposed on an alignment platen. The method includes the steps of generating in two insepection windows, comprised each of a matrix of photodiodes divided into quadrants i (i=1, 2, 3, 4), a reference image of the same dimensions as the image of each cross, and determining, for each quadrant and for each cross, "exposed" areas (S.sub.i.sup.+, S.sub.i.sup.+ ') corresponding to those portions of the image of the cross which extend beyond the outline of the reference image, and "masked" areas (S.sub.i.sup.-, S.sub.i.sup.- ') corresponding to those portions of the reference image which extend beyond the outline of the image of the cross. The values of said areas are used to compute the corrections (.DELTA.x, .DELTA.y; .DELTA.x', .DELTA.

Abstract: Disclosed is a method of fabricating a multichip interposer comprising an insulating support with thin film fine line metallization on one side thereof. A layer of masking material is adhered to in other side and selective areas of the masking material are removed in a desired pattern to expose areas of the support. The exposed areas of the support are then etched until the metallization is reached to form via holes which are subsequently filled with interconnecting metallurgy. Contact pads are then formed around each filled via hole.

Abstract: The rotator comprises a piezoelectric bender (4) pivotally supported (2, 3) at one end and carrying a means for being clamped (6) to which a "payload" (7) may be attached. The bender (4) has split electrodes to keep its ends parallel when energized. Normally engaging the means for being clamped (6) are clamping members (15, 17) attached to a pair of piezoelectric benders (10, 11) which are fixed in supports (12, 13) resting on a base plate (1).With the pair of benders (10, 11) energized, the means for being clamped (6) is released and energization of the central bender (4) results in the lifting of the payload (7) by one step. The means for being clamped (6) is then re-arrested and its pivot (2, 3) released by means of actuating the ends of bimorphs (10, 11) associated with clamping members 14 and 16 and the central bender (4) is permitted to stretch. The rotator is then prepared for the next step of rotation about the pivot (2). This embodiment permits rotation through about 15 degrees.

Abstract: Pinhole-free thin films deposited by glow discharge or plasma polymerization of organosilanes, organosilazones and organosiloxanes for use as reactive ion etch oxygen barriers in multilayer resist structures, of lift-off masks, for fabrication of semiconductor devices, such as integrated circuits. The process includes deposition of thin plasma polymerized organosilicon barrier film over a radiation insensitive polymeric base layer previously coated on a substrate, followed by thermal annealing of the plasma polymerized barrier layer, over which is then coated a radiation sensitive resist layer. After definition of the desired resist pattern by imagewise exposure and development, the image is etch transferred into the barrier layer by reactive sputter etching in a fluorine containing ambient, and subsequently transferred into the base layer, down to the substrate, in an oxygen plasma, during which time the plasma deposited film functions as an oxygen barrier.

Abstract: A current sharing modular power system including, in each module, an inverter circuit and means to determine the current to a common load from the module. A difference circuit is provided to determine the difference between the module supplied current and the average of the current supplied by the other modules. The difference is then utilized to vary the pulse width of the inverter output so that the pulses are wider if the current from the module is smaller than the current supplied by the other modules and the pulses are thinner if the current from the module is larger than the average current supplied by the other modules. The system also includes a voltage sense circuit to adjust the module operation to maintain a constant voltage output.

Abstract: An improved melting point temperature standard includes a well for receiving a temperature sensor to be calibrated. Surrounding the well is a cell with a crystalline material therein. A thermally conductive spacer contacts the outer cell walls. A thermal barrier contacts the spacer and a second thermally conductive member encircles the barrier. A heating/cooling element contacts the second thermally conductive member to apply heat or to cool it. Thermistors in the second thermally conducive member and the spacer are used by a control circuit to adjust the heat flow into the cell so that the crystalline material melts over a period of 7 to 8 hours making use of the temperature standard possible for many hours.

Abstract: A wide angle strip camera system which, in combination, includes a wide angle lens, having a curved conjugate focal surface, a first image-receiving surface, a first curved exposure slit disposed adjacent the first image-receiving surface; the lens, first image-receiving surface and first exposure slit being so mounted that a first curved strip at a constant preselected field angle in an object field is focused on the first image-receiving surface; a second image-receiving surface; a second curved exposure slit disposed adjacent the second image-receiving surface; fold flat elements interposed between the lens and the second exposure slit; the lens, fold flat elements, second image-receiving surface, and second exposure slit being so mounted that a second curved strip at a second constant preselected field angle in the object field is focused on the second image-receiving surface.