Abstract: A parallel to serial conversion circuit is disclosed. The circuit is used for converting parallel bits representing a plurality of words into serial bits. The circuit consists of storing means which comprises a plurality of word locations for temporarily storing the plurality of words at a parallel clock rate, and serialization means connected to the storing means for converting the parallel bits into serial bits at a serial clock rate. Each of the plurality of word locations is organized as a plurality of cells for storing each, one bit. Moreover the serialization means comprises parallel pointing means connected to the storing means for pointing to the plurality of words locations synchronously to the parallel clock, and serial pointing means also connected to the storing means for pointing to the plurality of cells synchronously to the serial clock.

Abstract: A multi-processor array organization is dynamically configured by the inclusion of a configuration topology field in instructions broadcast to the processors in the array. Each of the processors in the array is capable of performing a customized data selection and storage, instruction execution, and result destination selection, by uniquely interpreting a broadcast instruction by using the identity of the processor executing the instruction. In this manner, processing elements in a large multi-processing array can be dynamically reconfigured and have their operations customized for each processor using broadcast instructions.

Abstract: This apparatus and method controls and limits the flow of in-rush current and maintains a supply voltage to a peripheral device during power surges. The apparatus and method essentially isolate and limit in-rush current flow to an in-rush circuit comprising a capacitive load and series resistor connected directly to the power bus at one end and to a reference potential at the other end. A switching device is coupled to the series resistor. A current sensing circuit is coupled to the series resistor. During initial start-up or "hot plugging" of the device, a control circuit turns "off" the switching device causing the load to be charged from the power bus through the resistive device for a pre-selected time interval, after which the switching circuit is turned "on" to bypass the resistive device and connect the load and the peripheral device to the power bus.

Abstract: A method and system for optimizing data link occupation in a multipriority data traffic environment by using data multiplexing techniques over fixed or variable length data packets being asynchronously transmitted. The packets are split into segments including both a segment number and a packet number. The segments are dispatched, on a priority basis, over available links or virtual channels based on a global link availability control word indications, which control word is dynamically adjusted according to specific predefined conditions.

Abstract: A circuit and method provide a high valued resistance that is ideally used in low bandwidth filter and other signal processing applications. In one embodiment, an active device circuit includes first and second transistors, each having a gate, a source and a drain. The source voltages of the transistors change in response to an input signal voltage on an input terminal, and a current source constrains the gate to source voltages across the first and second transistors thus producing an output signal at an output terminal connected to the gate of the second transistor having a desired output resistance value based on the resistance across the drain and source terminals of the second transistor.

Abstract: A high speed data communication network is adapted to monitor and measure response time between a work station and a central host or processor coupled to the data communications network through a media, such as token ring, FDDI, Ethernet, etc. As the workstation communicates with the processor, a flag is set in a packet transmitted to the processor. The packet traverses the network to an application in the processor and a response returns which includes a flag. Each flag is a specific bit pattern. A programmable digital filter recognizes the flags and counts the number of bits on the network between the flags in the forward and reverse direction. By counting the bits on the media, when the flag moves in one direction or another, the total number of bits transmitted on the media between the two intervening flags is determined. The media speed is used as a clock. The number of bits counted divided by the media speed determines the response time with fine resolutions.

Abstract: A radio frequency (RF) local area network (LAN) adapter card for a personal computer conforms to the Personal Computer Memory Card International Association (PCMCIA) standard 2.0 (extended), providing a credit-card sized RF LAN communications terminal that plugs into the side of a personal computer, a laptop computer, a palmtop computer, and the like. The RF LAN adapter card includes a minimum height, broadband integrated antenna that provides a vertically polarized RF signal with good horizontal range. The combination of the antenna and its surrounding radome provide a high gain, omnidirectional radiation pattern that overcomes the parasitic distortions imposed by the close proximity of the personal computer housing. The adapter card housing includes internal RF shielding structures that shield the antenna from noise radiated by radio frequency signal circuits within the housing.

Abstract: A front cover assembly is provided for use with a touch sensitive display device. The touch sensitive display device includes a display such as a Cathode Ray Tube (CRT) or Liquid Crystal Display (LCD). The front cover assembly has a top cover, an infrared bezel and a piece of glass. The top cover is inserted into a mold along with the piece of glass. The top cover and glass are then held in place by a vacuum while polyurethane is injected to fill the void between the glass and the top cover and the mold. The polyurethane is injected using injection molding techniques. The polyurethane used must have the properties of flexibility, durability and must also be transparent to infrared light. The polyurethane provides a mechanical lock around the glass and top cover and thus the polyurethane compensates for the different rates of expansion and contraction of the glass and the top cover due to temperature variations in the ambient environment.

Abstract: This apparatus and method controls and limits the flow of in-rush current to a peripheral device coupled to a main power supply unit through a power bus and a ground bus. The apparatus and method essentially isolate and limit in-rush current flow to a capacitive load until operational current flow occurs to the peripheral device. A switching device is coupled to the power bus and the ground bus through a load. A resistive device is coupled to the power bus and the ground bus through the load. A control circuit is connected to the switching device. During initial start-up or "hot plugging" of the device, the control circuit turns "off" the switching device causing the load to be charged from the power bus through the resistive device until a predetermined condition occurs whereupon the switching circuit is turned "on" to bypass the resistive device and connect the load and the peripheral device to the power bus.

Abstract: An apparatus and a method for detecting a carrier signal of a phase shift keyed modulated signal. A first counter circuit generates a plurality of counts, with each count being a number of cycles of a reference frequency signal occurring between two consecutive rising edges of an intermediate frequency signal. A comparison circuit compares a first count of reference frequency cycles to a second count of reference frequency cycles when a difference between an initial count of reference frequency cycles and a first predetermined number is less than a second predetermined number. The first predetermined number represents a time period of one cycle of the nominal center frequency, and the first count and the second count respectively represent time periods of first and second cycles of a pair of consecutive cycles of the intermediate frequency signal. The comparison circuit generates a difference signal when a difference between the first count and the second count is less than a third predetermined number.

Abstract: A radio frequency (RF) local area network (LAN) adapter card for a personal computer conforms to the Personal Computer Memory Card International Association (PCMCIA) standard 2.0 (extended), providing a credit-card sized RF LAN communications terminal that plugs into the side of a personal computer, a laptop computer, a palmtop computer, and the like. The RF LAN adapter card includes a minimum height, broadband integrated antenna that provides a vertically polarized RF signal with good horizontal range. The combination of the antenna and its surrounding radome provide a high gain, omnidirectional radiation pattern that overcomes the parasitic distortions imposed by the close proximity of the personal computer housing. The adapter card housing includes internal RF shielding structures that shield the antenna from noise radiated by radio frequency signal circuits within the housing.

Abstract: A system and method monitor and control an Ethernet local area network, by monitoring bit gap distances between adjacent frames communicated by stations on the local area network. By analyzing the number of events for pre-selected bit gap distances, the network traffic characteristics can be characterized and interconnection paths between stations in the network can be altered.

Abstract: A high speed data communication network is adapted to monitor and measure response time between a work station and a central host or processor coupled to the data communications network through a media, such as token ring, FDDI, Ethernet, etc. As the workstation communicates with the processor, a flag is set in a packet transmitted to the processor. The packet traverses the network to an application in the processor and a response returns which includes a flag. Each flag is a specific bit pattern. A programmable digital filter recognizes the flags and counts the number of bits on the network between the flags in the forward and reverse direction. By counting the bits on the media, when the flag moves in one direction or another, the total number of bits transmitted on the media between the two intervening flags is determined. The media speed is used as a clock. The number of bits counted divided by the media speed determines the response time with fine resolutions.

Abstract: A communications adapter receives and transmits simultaneously packet and/or isochronous data between two interfaces; a network and a host bus system. The adapter stores the isochronous and packet data in receive and transmit queues configured in a FDDI RAM buffer. A controller manages the transfers of the data into and out of the queues. A local bus interacts with the system to provide descriptors of addresses in the system for transfers of data out of the queues to the system or the network. The controller is programmable to provide a variable threshold for the transfer of data between the queues and the system or the network. A systems interface unit handles the transfer of data to/from the system and allows data to bypass the queues and directly access the system or the network.