Abstract: Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requirements is the mesh connected computer. Such a computer becomes a massively parallel machine when an array of computers interconnected by a network are replicated in a machine. The nearest neighbor mesh computer consists of an N×N square array of Processor Elements(PEs) where each PE is connected to the North, South, East and West PEs only. The diagonal folded mesh array processor, which is called Oracle, allows the matrix transformation operation to be accomplished in one cycle by simple interchange of the data elements in the dual symmetric processor elements.

Abstract: The invention features a system and method to enable real-time establishment and maintenance of a standard of operation for a data communications network. The standard is a data set which includes network activity which is historically categorized by traffic type and by activity. The process begins with monitoring the network media or some network component over some period of time. The monitoring information is used to build benchmark data sets. The benchmark data sets contain a standard of operation for the network, which are historically categorized by either traffic type or activity. This standard of operation is constantly built by the intelligent monitoring facilities. After some period of time which is referred to as the benchmark data set refresh interval, the benchmark that was created is employed in a fashion to allow a determination as to whether the data that is taken from the current monitoring activity indicates normal network behavior.

Abstract: A phase shift modulator at the transmitter has a control input connected to a binary signal source. A high frequency carrier signal is applied to a carrier signal input of the modulator. The modulated carrier signal is transmitted to a receiver where it is mixed with a local oscillator frequency. At the receiver, a modulated signal is amplified by a limit amplifier to form the received signal into square wave pulses of a uniform height. The demodulator detects when the spacing between the edges of the square wave signal change in response to the phase shift modulation at the transmitter. When the spacing between the edges of the square wave IF signal is detected to be shorter than the normal spacing for a steady IF signal with no modulation, this signifies a first binary value. A longer than normal spacing between the edges of the square wave IF signal signifies a second binary value. Frequency drift compensation circuits are disclosed to overcome frequency variations in the carrier and the local oscillator.

Abstract: An apparatus and method reduces the number of rename registers for a floating point status and control register (FPSCR) in a superscalar microprocessor executing out of order/speculative instructions. A floating point queue (FPQ) receives speculative instructions and issues out-of-order instructions to FPQ execution units, each instruction containing a group identifier tag (GID) and a target identifier tag (TID). The GID tag indicates a set of instructions bounded by interruptible or branch instructions. The TID indicates a targeted architected facility and the program order of the instruction. The FPSCR contains status and control bits for each instruction and is updated when an instruction is executed and committed.

Abstract: An adaptive, active monitor invention is useful in detecting characteristic data patterns in messages on a high speed data network, such as starting delimiters, tokens, various types of frames, and protocol information. Such serial data streams include serial patterns of binary bits, and can also include serial patterns of multiple state symbols, such as in token ring networks and FDDI networks.The adaptive, active monitor includes two finite state machines (FSM) which are constructed to detect the occurrence of a characteristic data pattern having multiple component bit patterns. A first FSM is the predecessor FSM, and it is configured to detect the first occurring component pattern. A second FSM is called the successor FSM, and it is configured to detect the second occurring component pattern. The first FSM will send a starting signal to the second FSM, when the first FSM has successfully detected the first component pattern.

Abstract: A superscalar microprocessor chip includes a core processor with a distributed memory surrounding the perimeter of the processor. The distributed memory is arranged in sub-memory elements, each memory sub-element including check bits for each word stored in the sub-element. The number of check bits for each word is based upon the check bits required for a memory word formed from each word in each memory subelement, the number of ECC bits required for the combined word being less than the total number of bits available in the distributed memory. The difference in ECC bits and available bits provides spare bits which are used to route the ECC bits to ECC circuity positioned within the distributed memory for single error correction and double error detection. The position of the ECC circuity and the layout of the sub-memory elements with respect to the ECC circuitry are arranged to minimize the travel of the ECC bits for data correction or detection purposes, and does not adversely affect processor cycle time.

Abstract: A data processing system and method provide for sharing a partition of a memory in the system between a first task and thread and a second task and thread, so as to more efficiently enable adaptive sharing of data for local tasks or alternately copying of data into I/O buffers for remote tasks. The system and method automatically determine whether sharing has been established between two local tasks and if not, the system and method will adaptively copy data for messages to be transferred between the tasks.

Abstract: An array processor topology reconfiguration system and method enables processor elements in an array to dynamically reconfigure their mutual interconnection for the exchange of arithmetic results between the processors. Each processor element includes an interconnection switch which is controlled by an instruction decoder in the processor. Instructions are broadcast to all of the processors in the array. The instructions are uniquely interpreted at each respective processor in the array, depending upon the processor identity. The interpretation of the commonly broadcast instruction is uniquely performed at each processor by combining the processor identity for the executing processor, with a value in the instruction. The resulting control signals from the instruction decoder to the interconnection switch, provides for a customized linkage between the executing processor and other processors in the array.

Abstract: A massively parallel processor apparatus having an instruction set architecture for each of the N.sup.2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of PEs that contain instruction and data storage units, receive instructions and data, and execute instructions. The N.sup.2 structure should contain "N" communicating ALU trees, "N" programmable root tree processor units, and an arrangement for communicating both instructions, data, and the root tree processor outputs back to the input processing elements by means of the communicating ALU trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 PEs, identified as PE.sub.column,row, in a N root tree processor system, placed in the form of a N by N processor array that has been folded along the diagonal and made up of diagonal cells and general cells. The Diagonal-Cells are comprised of a single processing element identified as PE.sub.

Abstract: A plurality of processor elements (PEs) are connected in a duster by a common instruction bus to a sequencing control unit with its associated instruction memory. Each PE has data buses connected to at least its four nearest PE neighbors, referred to as its North, South, East and West PE neighbors. Each PE also has a general purpose register file containing several operand registers. A common instruction is fetched from the instruction memory by the sequencing control unit and broadcast over the instruction bus to each PE in the cluster. The instruction includes an upcode value that controls the arithmetic or logical operation performed by an execution unit in the PE on one or more operands in the register file. A switch is included in each PE to interconnect it with a first PE neighbor as the destination to which the result from the execution unit is sent.

Abstract: A parallel processing system and method is disclosed, which provides an improved instruction distribution mechanism for a parallel processing array. The invention broadcasts a basic instruction to each of a plurality of processor elements. Each processor element decodes the same instruction by combining it with a unique offset value stored in each respective processor element, to produce a derived instruction that is unique to the processor element. A first type of basic instruction results in the processor element performing a logical or control operation. A second type of basic instruction results in the generation of a pointer address. The pointer address has a unique address value because it results from combining the basic instruction with the unique offset value stored at the processor element. The pointer address is used to access an alternative instruction from an alternative instruction storage, for execution in the processor element.

Abstract: A parallel computer architecture supporting neural networks utilizing a novel method of separating a triangular array containing N processing elements on each edge into multiple smaller triangular arrays, each of dimension X and each representing a common building block processor group chip that can be interconnected for various size parallel processing implementations. The group chips are interconnected by a unique switching tree mechanism that maintains the complete connectivity capability and functionality possessed by the original triangular array of dimension N. For a given size K and X, K divisible by X, a triangular array containing K processor elements located on each edge of an equilateral triangular array is partitioned into K/X triangular arrays of dimension X and K(K-X)/2X.sup.2 square processor arrays of dimension X. An algorithm partitions a square array into two triangular arrays, each of dimension X.

Abstract: A system and method monitors and controls an asynchronous transfer mode (ATM) network having at least two ATM stations. An event driven interface is coupled to the ATM network for monitoring the selected ranges of contiguous non-empty cells and of contiguous empty cells communicated between the ATM stations and outputting count values for selected ranges of contiguous non-empty cells and of contiguous empty cells. An analysis computer is coupled to the output of the event driven interface, for analyzing the count values and outputting control signals. The control signals are used to reorder or change the time of transmission of data at a transmitting ATM station on the communications link, in response to the control signals.

Abstract: A continuous speech recognition and voice response system provides a natural sounding and effective interactive, speech-driven dialogue from a data processing system. A concatenation of words into phrases and sentences improves recognition and mimic natural language processing. The system uses speaker-independent, continuous-speech to initiate the playback of audio files. The system employs high-speed context switching to modify the active vocabulary and applies high-speed context switching to modify or activate Audio WAV voice response files. The system uses dialogue history to activate selected context, Baukus-Naur Form (BNF) grammars and WAV files and provides phrase or sentence long dialogue prompts to improve accuracy. The system also provides audio prompts to improve accuracy and provides speech-activated buttons to navigate between menus.

Abstract: Floating point hardware register set is not given to any user level thread unless it is required to perform floating point operations. Thus, for any non-floating thread, its context does not include the floating point hardware state. This effectively reduces the amount of information to be handled when threads are swapped in the processor. During the course of a thread's execution, at the first instance of an attempt by the thread to execute a floating point instruction, the "float-unavailable" exception occurs. This, in turn, invokes the microkernel's floating point exception handler. The function of this exception handler is to make floating point available to the thread that requires it. The exception handler dynamically allocates space for saving the thread's floating point registers, initializes the registers, and turns on the "float-available" bit in its machine state register. Once a thread obtains floating point context, it continues to have it for the remainder of its life.

Abstract: A high performance, real-time control sequencer is disclosed which incorporates a unique state matrix logic. This real-time control sequencer performs rapid resolution of control processed state transitions and the required control actions as a function of detected external events and the current control process state. The control sequencer's micro-instructions present event and current state data as inputs to a state matrix logic and initiate state matrix operations. The state matrix, in turn, outputs data defining and initiating the next control process state, required process control actions to be performed by the control sequencer microcode, process status, and event response or control output data. The real-time, event-driven data processor invention provides greater flexibility for reconfiguring event patterns to be detected and responses desired.

Abstract: An adaptive, active monitor invention is useful in detecting characteristic data patterns in messages on a high speed data network, such as starting delimiters, tokens, various types of frames, and protocol information. Such serial data streams include serial patterns of binary bits, and can also include serial patterns of multiple state symbols, such as in token ring networks and FDDI networks.The adaptive, active monitor includes two finite state machines (FSM) which are constructed to detect the occurrence of a characteristic data pattern having multiple component bit patterns. A first FSM is the predecessor FSM, and it is configured to detect the first occurring component pattern. A second FSM is called the successor FSM, and it is configured to detect the second occurring component pattern. The first FSM will send a starting signal to the second FSM, when the first FSM has successfully detected the first component pattern.

Abstract: A workstation manages and controls a plurality of communication networks using different protocols coupled to a common bus. A programmable digital filter connected between the workstation and the networks examines frame information using real time calculation for identifying protocols in the frames. The filter identifies and counts addresses, security conditions and other information of interest on the bus and occurring in the networks. The protocol, address, security data and other information of interest counted by the filter are stored in storage for access by an interpreter. The stored data for the networks accessed by the interpreter is compared to network models for identification of traffic problems and conditions and load balancing. The network interpreter contains a graphical user interface which displays selected information at a monitor for an operator to examine and initiate corrective action by initiating commands.

Abstract: The oscillator at the sending node of a wireless digital network, generates a carrier signal, starting at a first instant. A modulator coupled to the oscillator performs phase shift modulating of the carrier signal with an input signal. A spoiler signal generator is coupled to the modulator, for providing a spoiler signal as the input signal, starting at the first instant and continuing for a first duration which is longer than a period needed for the oscillator to achieve stable characteristics. A transmitter is coupled to the modulator at the sending node, for transmitting a wireless radio signal representation of the carrier signal phase shift modulated with the spoiler signal to a receiver at a receiving node. The spoiler signal in the modulated carrier signal interrupts the periodic characteristic of the pulses, and thereby prevents the carrier sensor from detecting the carrier signal.

Abstract: A data processing system and method manages the recognition of text characters in a plurality of document images. The documents are predefined forms having a plurality of fields in which text characters are to be recognized. A form definition data set is used to specify various characteristics of the fields on the form such as their locations. A data capture priority value is specified in the form definition data set for at least some of the fields. This priority is used to manage the workload of the character recognition process. When a large number of document form images have been received by the system, they can limit the backlog volume and maintain a desired throughput for character recognizing the forms by reducing the number of fields which are character recognized on each form. By using the data capture priority value for each field, the character recognition processor can be controlled to omit processing or perform faster, lower-quality processing of low priority fields.