Abstract: When fetching a load value for a load instruction results in a cache miss, the load instruction and any load-dependent instructions may be speculatively executed with a predicted load value and retired before the missing cache line is retrieved and the actual load value is determined. By storing the predicted load value in a table, when the actual load value is determined it may be compared with the predicted load value from the table. If the predicted load value was incorrect, the load and load-dependent instructions may be re-executed with the actual load value. A compiler may determine which load instructions are highly predictable and likely to result in cache misses, and designate only those load instructions for speculative execution.

Abstract: A method is provided for forming a waveguide in a printed circuit board. This may include forming a trench in a printed circuit board substrate and forming at least one metalized surface along the trench. A metalized capping surface may be provided over the trench so as to form the waveguide structure.

Abstract: An offset line to substantially cancel the capacitive coupling effects of a select line to a memory cell. When the select line transitions to cause a stored memory state in the memory cell to be placed onto a sense line, capacitive coupling from the select line to the sense line is substantially cancelled by capacitive coupling, of an opposite polarity, from an offset line to the sense line. Without the opposing effects of the offset line, the capacitive coupling from the select line would raise the pre-charge voltage level on the sense line, which would then require a longer time to discharge down to the input threshold of a sense gate that detects the stored state that was in the memory cell.

Abstract: The sloped edges of patterned photoresist material are made more vertical by treating the exposed and developed photoresist pattern to an edge correction process. A layer of acid-based material is deposited on the photoresist pattern. The layer is then exposed to acid-neutralizing light to create a top-to-bottom gradient of acidity. The structure is then exposed to heat to cause the acid to diffuse into the edge of the photoresist in amounts roughly proportional to the gradient. A subsequent development process removes the acid-based layer and also reshapes the photoresist edge in proportion to the acid diffusion, leaving a more vertical edge.

Abstract: A resist material used to mask an underlying layer during an etch process is subjected to ion implantation to harden the resist material against damage from the etch process. In a particular embodiment, the resist material is compatible with exposure to 193 nm radiation for patterning the resist material.

Abstract: Briefly, in accordance with one embodiment of the invention, a method by which one or more ways of a cache may be locked so that they are not overwritten with data. Further, the ways of a cache that are locked may be given higher priority than the most recently used or accessed ways.

Abstract: A micro-code sequence to reduce the rate of change of current required by a processor coming out of a sleep mode when the processor clock is resumed. After stopping the instruction fetch unit, an instruction with a long latency, or execution time, can be initiated by the micro-code before the processor clock is stopped to enter a sleep mode. When the sleep mode is exited by resuming the processor clock, the instruction with the long execution time is completed before restarting the instruction fetch unit. This prevents a portion of the processor circuitry from resuming operation immediately when the clock is resumed, which also delays some of the current demands made by that portion of the circuitry. This creates a more gradual increase in the current required by the processor when exiting a sleep mode.

Abstract: A package substrate having a finger projection that is either an elevated or removably covered bond finger. The finger portion includes a portion to remain uncovered by a die and an underfill material when the package substrate is coupled to the die. A second portion of the finger projection may allow the first portion to remain uncovered as indicated.

Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

Abstract: Treatment of dielectric material includes using a directed energy to break bonds in a dielectric material and a reactive gas to repair those bonds with an element of the reactive gas. The treated dielectric material may exhibit greater mechanical strength without a significantly greater dielectric constant. A treatment reactor including a directed energy source apparatus and a delivery mechanism to deliver the reactive gas is also described.

Abstract: A linear systolic array Montgomery multiplier circuit that concurrently processes two separate Montgomery multiplications on alternate clock cycles, without a requirement to have any common parameters between the two multiplications. Multiples of two different parameters are stored in storage elements for each multiplication. Two sets of these multiples, one set for each of the two multiplications, are stored in separate storage banks and accessed on alternate clock cycles by each processing element in the array. Two sequences of control codes for the two multiplications are interleaved as they are fed into a first processing element.

Abstract: Leakage current from non-selected memory cells is substantially eliminated by placing a negative voltage on the selection line of the non-selected cells. This negative voltage on the gate of the access transistors in the cells reduces the leakage current that would otherwise leak onto a shared sense line if the selection line were biased at 0 volts. In one embodiment the pre-charge voltage on the affected sense line is reduced so that the difference between the pre-charge voltage and the negative voltage does not exceed the design voltage of the transistors in the memory cells.

Abstract: A device controller can have multiple device performance states (DPS), which represent different levels of performance vs. power consumption during operation. The device controller can include a DPS status register that can be read by a processor, to indicate the current DPS, and a DPS control register that can be written by the processor, to change the current DPS to a desired DPS. The controller may also have a processor performance state (PPS) status register which can be used to affect the desired choice of DPS based on the performance state of the processor. Each of the registers can be accessed by the device driver for that device controller. The DPS of multiple devices can be coordinated to achieve an improved system-level reduction in power consumption, while maintaining sufficient operational capability.

Abstract: A round robin bus arbitrator that prevents bus starvation caused by an inbound buffer becoming full and forcing repetitive retries by an agent. The arbitrator performs a rotating scan of the request lines of multiple potential bus requesters. When a request is detected, the arbitrator stops, grants the request, and resumes scanning after the requester takes control of the bus. If the data buffer on a write operation becomes full and cannot accept any more data, a signal so indicating is sent to the arbitrator. The arbitrator then stops scanning, or refuses to resume scanning if it is already stopped, until the buffer indicates it is no longer full. The next requester that is granted the bus is therefore not confronted with a full buffer, and not thereby forced to abort the request and make a retry. The invention avoids bus starvation caused by a second bus requestor repeatedly being given a retry response because the buffer is repeatedly filled up by an earlier bus requestor.

Abstract: Embodiments of the invention are disclosed that include a low power memory and a low power data path.

Abstract: A write cache that reduces the number of memory accesses required to write data to main memory. When a memory write request is executed, the request not only updates the relevant location in cache memory, but the request is also directed to updating the corresponding location in main memory. A separate write cache is dedicated to temporarily holding multiple write requests so that they can be organized for more efficient transmission to memory in burst transfers. In one embodiment, all writes within a predefined range of addresses can be written to memory as a group. In another embodiment, entries are held in the write cache until a minimum number of entries are available for writing to memory, and a least-recently-used mechanism can be used to decide which entries to transmit first. In yet another embodiment, partial writes are merged into a single cache line, to be written to memory in a single burst transmission.

Abstract: Programming a reference voltage in a reference cell of a charge-based memory to a level that will maximize the predicted operational life of the memory, based on the application-specific predicted usage profile of the memory and the effects of that usage profile on the leakage curves of the various memory states. The different states of a memory cell may have different leakage rates, based on operational and environmental considerations, causing the cell to fail prematurely in one state, while having significant remaining life in the other state(s). The operational life of the memory can be increased by adjusting the reference threshold voltage so that the faster-leaking sate will last longer before failure occurs. Maximum operational life can be achieved by setting the reference voltage to maximize the predicted time-to-failure of the state with the shortest predicted time-to-failure.

Abstract: A first signal routing layer may be formed on a first surface of a printed circuit board (PCB). An array of interconnections may formed on the first surface of the PCB, the array of interconnections comprising at least one padless via formed within the PCB, the at least one padless via extending from the first signal routing layer to at least one conductive plane and/or a second signal routing layer. The at least one padless via may be in electrical contact with the at least one conductive plane and/or a conductive trace on the second signal routing layer. A component may be attached to the PCB, with a solder interconnection between the at least one padless via and a contact pad on a bottom surface of the component. The component may be, for example, an electronic component such as a ball grid array (BGA) component or a leadless surface mount component.

Abstract: The present invention is in the area of memory architecture. More particularly, the present invention provides a method, apparatus, machine-readable medium, and system reduce leakage current in memory. Embodiments may take advantage of the reverse bias characteristic of circuit elements, such as the reverse gate-to-source bias characteristic of a transistor, within the memory to limit leakage and provide for a leakage tolerant data storage technique. Embodiments may also enable the reverse bias characteristic of circuit elements, such as the reverse gate-to-source bias characteristic of a transistor, to be taken advantage of by sourcing charge from data storage elements.

Abstract: A Montgomery multiplier circuit with a chain of processing elements uses less circuit logic in each processing element by propagating an initial parameter through registers used for other purposes. An accumulation register in each processing element is used to propagate the initial parameter through the chain. In one embodiment the initial parameter is first propagated through address registers until it reaches the end of the chain, and is then looped back through the accumulation registers in the reverse direction. In one embodiment, multiples of at least one parameter used in a Montgomery multiplication are pre-calculated in the processing elements of the Montgomery multiplier using the same logic elements used in performing the Montgomery multiplication.