Abstract: A multistage voltage multiplying circuit for single chip passive RF tags is provided, wherein the parasitic capacitance of the diodes of each stage of the voltage multiplying circuit is much less than the parasitic capacitance of the diodes of the preceding stage.
Type:
Grant
Filed:
February 22, 2005
Date of Patent:
January 2, 2007
Assignee:
Intermec IP Corp.
Inventors:
Vijay Pillai, Harley Kent Heinrich, Rene D. Martinez