Abstract: Temporary adjustable bipolar lead including an inner lead and an outer coaxial lead. A self-sealing lead introducer head at a junction of the inner lead and outer lead provides for takeoff of the end of the outer coaxial lead. The inner lead is in slidable engagement with the outer lead through a hole in a diaphragm of the lead introducer head.

Abstract: The lead anchoring bobbin for containing a transvenous pacing lead at an entry site in human tissue and including a grooved bobbin and buttons which frictionally engage and detain the lead on either side of the bobbin. The lead anchoring bobbin is made of medical silicone rubber or like material.

Abstract: Tine protector which protects a plurality of outwardly angular extending tines from an electrode of a pacing lead. The tine protector includes four sides and a bottom where two of the opposing sides include a first round hole in one side, and a second round hole joined to a longitudinal vertical slit in the other side. The electrode frictionally engages into the first hole, and the other electrode or lead of the pacing lead frictionally engages down through the slit and into the second hole. The tines are protected by their close proximity to these two opposing sides.

Abstract: Terminal pin which engages into a wire coil of a transvenous pacing lead and mechanically attaches to the wire coil with a metal crimping sleeve which engages over the wire coil. The terminal pin includes a tapered distal end portion from an outward radial shoulder in a midportion of the terminal pin to the distal end of the terminal pin. A stylet easily passes through a longitudinal hole extending through the terminal pin and into the wire coil of the transvenous pacing lead.

Abstract: Stylet including a stylet knob, a stylet wire, and a swaged stylet wire retaining sleeve over the stylet wire which engages within the stylet knob providing for controlled length and straightness of the stylet wire and mating within the long thin walled stylet knob.

Abstract: Lead connector for use between an external pulse generator and a pacing lead. The lead connector includes elongated geometrical spaced connector pins which plug into connector terminals of the pulse generator and a hole accepting the connector end of the pacing lead. A case of the lead connector supports a pressure plate which is spring biased against a thumbscrew and engages a connector of the pacing lead against the connector pins of the lead connector.

Abstract: Apparatus for use within a virtual memory data processing system offering a way of protecting data used at one interrupt level state from unauthorized use at another interrupt level state. A virtual memory data processing system permits a computer program to specify relative (or virtual) addresses rather than physical (or real) addresses. Most practical virtual memory data processing systems utilize a Virtual Address Translator (VAT), often called a Directory Look-Aside Table (DLAT). The VAT contains a plurality of internal conversion tables which perform virtual address to real address translation. A binary code, called the Interrupt Level Code (ILC), is appended to the virtual address of entries within the plurality of internal conversion tables within the VAT to permit the VAT to translate virtual addresses to real addresses only if the present Central Processing Unit (CPU) interrupt level state corresponds to the interrupt level state denoted by the ILC within the VAT.

Abstract: A method of and an apparatus for selectively isolating digital data bus drivers from digital data busses for fault recovery and diagnostic purposes. The digital data bus drivers may be either transistor-transistor logic (TTL) or emitter coupled logic (ECL). For TTL digital data bus drivers, the input voltage (V.sub.CC) is supplied via a switching power transistor. For ECL digital data bus drivers, the ground connection (V.sub.CC1) is made via a switching power transistor. In either case, the switching power transistor is turned on and off in response to one binary bit in an isolation register coupled to the power transistor via an open collector gate or electromechanical switch. By supplying the V.sub.CC (for TTL) or V.sub.

Abstract: Apparatus for determining the next data word of a requested block of data words in interlaced rotating mass memories to enable transfer of the requested block from other than the first word in the block to reduce the effective average latency. The system assumes the use of a memory storage element which is read in a serial rotational fashion (e.g., drum, disk, charge coupled device, etc.). The present invention compares the address of the data requested by a Central Processor Unit (CPU) with the address from the interlaced memory storage element that indicates its present rotational position. From these addresses, it computes the address of the next accessible cell within the requested block and transfers that address to the CPU to enable it to access the requested block at the earliest possible time.

Abstract: An apparatus for enabling a central processing unit (CPU) to directly read the address transferred to a memory module to permit the CPU to test the address circuitry of the memory module without actually referencing an addressable location of the memory array within the memory module. A status register located within the memory module has two bit positions assigned to controlling the closed loop address capability. If the two assigned bit positions contain binary zeroes, the memory module operates normally by using each address received to address one addressable location of the memory array of the memory module. If one of the assigned bit positions contains a binary one, subsequent read commands cause the memory not to access the memory arrays but to return the portion of the address corresponding to the bit position containing the binary one (i.e.

Abstract: Apparatus for providing a closed loop data path within a memory module to enable a central processing unit (CPU) to test the error correction circuitry of the memory module under software control without the necessity of accessing the memory arrays within the memory module. The memory module has error correction circuitry providing single bit correction/double bit detection. The error correction circuitry generates an error code which is appended to each data word upon being written into the memory array of the memory module. The error correction circuitry uses the error code to detect and correct errors in each data word read from the memory array of the memory module. A status register within the memory module stores control and status information for communication between the central processing unit and the memory module. Two bit positions of the status register are dedicated to closed loop error correct. If both bit positions contain binary zeroes, the memory module operates normally.

Abstract: A method of and an apparatus for distinguishing between transient and solid errors within a single-error-correcting semiconductor memory storage unit (MSU) comprised of a plurality of large scale integrated (LSI) bit planes and for notifying the associated data processing system of required maintenance action. The method utilizes an error logging store (ELS) that is comprised of a plurality of memory error registers one for each separately associated word group within the MSU. Each memory error register contains storage for: (1) the Error Correction Code (ECC) defined, failing bit position; (2) the single bit error counter; (3) the multiple single bit error tag; and (4) the multiple bit error tag. Upon detection of an error within a word group, the associated memory error register is accessed to determine the history of previously detected errors within that word group.

Abstract: An apparatus for and a method of providing error correction in a random access memory (RAM) using two dimensional parity checking. The RAM and a parity register are initialized such that the parity register represents the proper (i.e., either odd or even) longitudinal parity (i.e., parity for each individual bit position of all addressable locations) for the RAM. The parity register is updated each time an addressable location of the RAM is written into to maintain proper longitudinal parity. The horizontal or word parity of each addressable location is checked each time that addressable location is read. At the observance of improper word parity, a memory controller halts normal activity and recomputes the longitudinal parity by reading each addressable location of the RAM. A logical comparison (exclusive-or) of the current longitudinal parity at the time of observance of improper word parity with the recomputed longitudinal parity reveals the failing bit position.

Abstract: An integrating Input/Output (I/O) element containing an I/O processor that provides a computer with those functions normally associated with an I/O processor (or I/O controller) but which possesses architectural features to prevent compromise (i.e., unauthorized dissemination) of data in a multi-level secure environment. The I/O processor is programmable via an internal instruction memory which cannot be altered by the I/O processor and which cannot be accessed by any other portion of the computer (i.e., Central Processor Unit). The instruction memory is segmented providing a separate segment for each I/O channel. The instructions used to control each I/O channel are stored within the segment of instruction memory allocated to that I/O channel. A secondary memory, called the hand-off memory, is a read/write memory accessible by the Central Processor Unit (CPU) as well as the I/O processor.

Abstract: An integrating processor element containing a data processor that provides a computer with those functions normally associated with the Central Processor Unit (CPU) but which possesses architectural features to prevent compromise (i.e., unauthorized dissemination) of data in a multi-level secure environment. The data processor executes instructions from an internal instruction memory which cannot be altered by the data processor and cannot be accessed by the I/O processor (i.e., I/O controller). The instruction memory is segmented providing a separate segment for each discrete level of secure data to be processed. Each computer program is stored in the segment corresponding to the highest level of security of the data it will use. A second memory, called the hand-off memory, is a read/write memory accessible by the I/O processor as well as the data processor. The hand-off memory is also segmented by security level.

Abstract: Apparatus for measuring the rate of occurrence and duration of digital events through the technique of multiple sampling at times random to the occurrence of the digital events. The digital events to be sampled are represented as the presence or absence of binary ones or zeroes that can be sensed in a subject conductor at a given point in time. Since the probability of sensing a binary state of true or false at any particular but randomly determined time is a function of the duty cycle, sensing the binary state of or sampling a given digital event a given number of times produces a correspondingly statistically significant measure of the duty cycle of the digital event. The greater the number of samples, the greater the confidence in the measure of the duty cycle. The number of samples necessary to evoke a given confidence level is determined through the use of basic statistics. The point in time at which sampling occurs must be random to permit statistical validity.

Abstract: A read-only memory, adapted to be addressed by the operation code portion of a computer instruction word, stores at addressable locations therein a flag indicating whether a particular combination of operation code bits is a valid combination.

Abstract: An improvement to a semiconductor memory subsystem containing single bit error correction/double bit error detection (SBC/DBD) which provides correction of double bit errors through the utilization of a modest amount of additional circuitry. The present invention accomplishes this result through the technique of sequentially complementing each double bit pair within the semiconductor memory subsystem data word determined to contain a multiple error and rechecking the modified data word with the existing SBC/DBD circuitry, one double bit pair at a time, until it is determined by the SBC/DBD circuitry that such double bit pair complementing has corrected the double bit error.