Abstract: An efficient request-reply protocol for a client-server communication and data processing model. Under the novel protocol, a client sends a Request to a server and awaits a Reply. If the Reply is not sent before expiration of a timeout period in the client, the client sends a second Request. The server provides a conditional Acknowledge if a second Request is received from the client. Thereafter, the client waits for the server to transmit a Reply without the client sending additional Requests. Under normal conditions, the inventive protocol performs as well as the best prior art protocol (the optimistic model), while under abnormal conditions, the inventive protocol performs better than the optimistic protocol and only slightly worse than the prior art pessimistic protocol. Since normal conditions should prevail for a substantially longer amount of time than abnormal conditions, the present invention provides better average performance than either prior art client-server protocol.

Abstract: A method and apparatus for analyzing each microinstruction in a microinstruction-based electronic circuit having a plurality of registers to determine which registers in a processing cycle are not involved in the processing cycle, and preventing those registers from being clocked during such processing cycle. Hence, inactive registers during a processing cycle do not consume power at the level of active registers, thus lowering overall power usage by any system employing such gated-clock registers.

Abstract: A method and apparatus for using multiple code rates for forward error correction in a cellular digital data radio communication system. Each base station broadcasts a quantity called the power product (PP), which is equal to the base station transmit power, P.sub.BT, multiplied by the power level received at the base station, P.sub.BR. For a mobile unit to determine its appropriate transmit power, P.sub.MT, requires measuring the power received, P.sub.MR, at the mobile unit and performing the following calculation: P.sub.MT ==PP/P.sub.MR. When channel path loss is large, it is possible that the power control calculation will return a value greater than the maximum transmit power capability of the mobile unit. In such a case, the mobile unit selects a lower code rate. Base station receiver sensitivity improves as the code rate decreases, so the result is similar to increasing the transmitter power. In the preferred embodiment, the invention uses 3 different code rates.

Abstract: A redundant array storage system in which a reserved area of a multiplicity of data storage units can be reliably synchronized, even if the synchronization cycle is interrupted by an unforeseen event or situation, such as sudden loss of power to the system or a component failure. By maintaining two groups or partitions of data storage units and updating only one group at a time, and by having a global table which provides information regarding which group of storage units is being updated, the present invention allows the system to reliably determine which of the data storage units maintain valid data in their reserved area and to conform the reserved areas of the other group of data storage units to the valid values, without the use of additional hardware devices.

Abstract: An array controller including a DATA-RAM and a SHADOW-RAM. Both the DATA-RAM and the SHADOW-RAM are coupled to a first and second memory interface. Each memory interface has the ability to independently communicate the contents of the SHADOW-RAM over a controller-controller data link to at least one other similar array controller. The memory interface also interfaces the DATA-RAM and the SHADOW-RAM to a CPU, the data storage units of the RAID system, and the controller processor. Write data received from the CPU is stored in the two independent memories in order to ensure that pending Write data (i.e., Write data that has not yet been written to the RAID system, including any copyback cache device) will not be lost. In addition, the two memory interfaces provide redundant access routes which allow Write data to be retrieved by another array controller if the controller processor fails.

Abstract: A redundant array storage system including storage units divided into two logical arrays. The redundant array storage system further includes a plurality of array control units which are all fully utilized to control data transfers between the logical arrays and a central processing unit, each controller being capable of taking over the task of a failed controller. In normal operation, each redundant array controller may only access data stored in a logical array assigned to that controller. If the other redundant array controller fails, the remaining controller may access the data stored in the logical array assigned to the failed controller only through a secondary control process that is independent from the primary control process of the remaining controller. Thus, the invention prevents parity data associated with user data placed in storage from being corrupted by attempts of two or more array control units to access the same redundancy group of data concurrently.

Abstract: A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, Read-Modify-Write operations are performed during idle time. In a second embodiment of the invention, normal Read-Modify-Write operation by the RAID system controller continue use Write data in the controller's buffer memory. In a third embodiment, at least two controllers, each associated with one copyback cache storage unit, copy Write data from controller buffers to the associated copyback cache storage unit.

Abstract: A redundant array storage system that can be configured as a RAID 1, 3, 4, or 5 system, or any combination of these configurations. The invention includes a configuration data structure for addressing a redundant array storage system, and a method for configuring a redundant array storage system during an initialization process. The redundant array storage system includes a set of physical storage units which are accessible in terms of block numbers. The physical storage units are each configured as one or more logical storage units. Each logical storage unit is addressed in terms of a channel number, storage unit number, starting block number, offset number, and number of blocks to be transferred. Once logical storage units are defined, logical volumes are defined as one or more logical storage units, each logical volume having a depth characteristic. After the logical volumes are defined, redundancy groups are defined as one or more logical volumes. A redundancy level is specified for each redundancy group.

Abstract: An environment sensing/control circuit for use in conjunction with an electronic subsystem. The invention is capable of sensing and controlling conditions of the environment of the subsystem. The invention is capable of being implemented as a stand-alone device or replicated numerous times in an integrated circuit. The invention identifies changes including intermittent changes, in the environment of the subsystem from a reference state, the reference state being dynamically determined by a processor. Upon detecting such a change, the invention signals the processor. The invention can also serve as a flexible interface for control signals from the processor to the subsystem.