Abstract: A dual track SAW reflector filter (150) including a first track (152) and a second track (154). The first track and the second track (152, 154) include an input transducer (156, 164), an output transducer (158, 166), first reflectors (160, 168) and second reflectors (162, 170). The reflectivity function of the first reflectors (160, 168) and the second reflectors (162, 170) are equal in magnitude and opposite in phase. The input transducers (156, 164) have the same polarity and the output transducers (158, 166) have opposite polarities. Surface acoustic waves produced by the input transducers (156, 164) and received directly by the output transducers (158, 166) are in phase and cancel at the output transducers (158, 166). Surface acoustic waves reflected by the reflectors (160, 162, 168 and 170) are in phase and add at the output transducers (158, 166).

Abstract: An EUV radiation source that creates a stable solid filament target. The source includes a nozzle assembly having a condenser chamber for cryogenically cooling a gaseous target material into a liquid state. The liquid target material is filtered by a filter and sent to a holding chamber under pressure. The holding chamber allows entrained gas bubbles in the target material to be condensed into liquid prior to the filament target being emitted from the nozzle assembly. The target material is forced through a nozzle outlet tube to be emitted from the nozzle assembly as a liquid target stream. A thermal shield is provided around the outlet tube to maintain the liquid target material in the cryogenic state. The liquid target stream freezes and is vaporized by a laser beam from a laser source to generate the EUV radiation.

Abstract: A collector optic assembly for a EUV radiation source. The collector optic assembly includes an elliptical meniscus having a reflective Si/Mo coating for collecting and reflecting EUV radiation generated by the source. The meniscus is machined from a single piece of silicon. The collector optic assembly further includes a heat exchanger that includes cooling channels through which flows a liquid coolant. The heat exchanger is fabricated from a plurality of machined silicon sections fused together by a glass frit bonding process. The meniscus is fused to a front side of the heat exchanger by a glass frit bonding process. A liquid coolant inlet manifold and a liquid coolant outlet manifold are also each machined from a single silicon block and are mounted to a back side of the heat exchanger.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter (18) employs a suitable mixer (28), BPA (32), attenuator (34), and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC (20). A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter (18) employs a suitable mixer (28), BPA (32), attenuator (34), and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC (20). A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels. In one embodiment, the frequency down-conversion is performed in a single down-conversion process, and the ADC (20) employs delta-sigma processing to provide digital conversion over the complete frequency band.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter (18) employs a suitable mixer (28), BPA (32), attenuator (34), and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC (20). A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels.

Abstract: An apparatus for and a method of determining the envelope of a complex baseband signal having an in-phase component I and a quadrature component Q by determining (I2+Q2)½ for sampled values of the baseband signal. The maximum and minimum values of I and Q are detected by detecting the larger of I and Q in a first detection circuit (18) and the smaller of I and Q in a second detection circuit (20). A value x=½{(the detected minimum value)÷(the detected maximum value)}2 is calculated in a first calculation circuit (22). The value of (I2+Q2)½ is then calculated based on the value of x. In a first embodiment the value of (I2+Q2)½ is calculated in a second calculation circuit (24, 26, 28, 30, 32, 34, 36, 38) as the (the detected maximum value)×(1+x)/2+½(1+x−x2+x3−x4+x5−x6).

Abstract: A DAC including a first switch and a second switch. The first switch receives a digital signal to be converted, and the second switch receives the digital signal delayed by one-half of a clock signal. A third switch receives a current signal from a current source and the clock signal. The third switch alternately switches the current signal to the first and second switches so that when the clock signal is positive, the current signal is applied to the first switch and when the clock signal is zero, the current signal is applied to the second switch. The first switch will output the current signal during the first half of the clock cycle to a first output or a second output, and the second switch will output the current signal during the second half of the clock cycle to the first output or the second output.

Abstract: A transmitter circuit for transmitting a sine wave modulated with digital data, where the sine wave includes a clock signal, and a receiver circuit for demodulating the transmitted sine wave, where the receiver circuit extracts the clock signal and the digital data from the sine wave. The transmitter circuit includes digital logic components that allow the transmitted sine wave to include at least one bit per cycle of the sine wave, and the receive circuit includes digital logic components that allow the clock signal and the digital data to be extracted from the sine wave. In various embodiments, the transmitted sine wave includes one bit per cycle, one bit per half cycle, multiple bits per cycle and multiple bits per half cycle.

Abstract: A thermal imaging system for detecting cracks and defects in a structure. An ultrasonic transducer is coupled to the structure through a malleable coupler. Ultrasonic energy from the transducer causes the defects to heat up, which is detected by a thermal camera. A control unit is employed to provide timing and control for the operation of the ultrasonic transducer and the camera.

Abstract: A decoder for decoding data transmitted between superconductor circuits. Interleaved data and clock pulses are applied to a clock input of a flip-flop circuit and one input of an AND gate. The output of the flip-flop circuit is a clock signal, and is applied to a delay circuit to be put in phase with the data pulses in the interleaved signal. The delayed clock signal is then applied to the other input of the AND gate, so that when a data pulse occurs in the interleaved signal it aligns with a clock pulse and is outputted from the AND gate. The clock signal from the flip-flop circuit is also sent to the input of the flip-flop circuit through a delay circuit that delays the signal more than one half of the clock period and less than one clock period. This delayed clock signal sets the flip-flop circuit to the “1” state after the data pulse in the interleaved signal are input to the flip-flop circuit so that the data pulses are not outputted from the flip-flop circuit.

Abstract: A cascadable divide-by-two binary counter circuit (120) that has particular application for use as a synchronous divider circuit (50, 54) in a phase lock loop (26). The counter circuit (120) employs a D flip-flop (122) that receives a D input and provides a Q output. A first AND gate (124) is responsive to a P input and a Q input, where the Q input is the output from a preceding counter circuit and the P input is the state of all of the preceding counter circuits. The output of the AND gate (124) is applied to an exclusive-OR gate (126) along with the Q output of the flip-flop (122). The output of the exclusive-OR gate (126) is applied to one input of a second AND gate (128). The other input of the second AND gate (128) is a reset signal and the output of the second AND gate (128) is the D input of the flip-flop (122). A decoder (142) is programmed to provide the reset signal when the desired count is reached.

Abstract: A superconducting oscillator/counter analog-to-digital converter (50) that provides simultaneous in-phase and quadrature-phase of an RF input signal. The RF input signal is converted to a series of SFQ input pulses by a superconducting voltage controlled oscillator (12). A clock circuit (26) generates a series of SFQ clock pulses. The SFQ input pulses and the SFQ clock pulses are applied to a pulse repulsion circuit (52) that outputs the SFQ input pulses and the SFQ clock pulses spaced apart in time. In one embodiment, the pulse repulsion circuit (52) includes two Josephson transmission lines (60, 62), where the magnetic coupling between the lines (60, 62) provides the SFQ pulse repulsion.

Abstract: An apparatus for and a method of generating an envelope predistorted radio frequency signal. A complex baseband signal, having an in-phase component I and a quadrature component Q, is sampled and filtered. The magnitude uk of each complex baseband sample pair is determined by the square root of the sum of the squares of the in-phase component sample and the quadrature component sample. A distortion factor Dk, is determined based on a scaled value of the inverse hyperbolic tangent or archyperbolic tangent (“atanh”) of the baseband sample magnitude divided by that scaled sample magnitude. Each sample of the in-phase component Ik and of the quadrature component Qk is multiplied by the corresponding distortion factor Dk so as to provide predistorted components. The predistorted components are then combined to provide a predistorted baseband signal.

Abstract: Demodulating a DPSK encoded data signal. The received signal has a symbol tracking value determined in a synchronization circuit. Doppler error in the signal is estimated. The signal, the symbol tracking value, and the estimated Doppler error are applied to a demodulator within which the signal is multiplied by a signal at a frequency which is the negative of the estimated Doppler error to remove that Doppler error. The resulting signal is filtered and decimated and normalized to generate the arctangent of the in-phase and quadrature components of the baseband signal. This arctangent signal is stripped of phase angle modulation and applied through loops to remove derivatives of the input phase signal. The arctangent and the resulting angles are mapped in a nearest neighbor map circuit, and the difference between successive angles is applied to a gray code to binary mapping circuit which detects the encoded data.

Abstract: An EUV radiation source (12) that generates a sheet (36) of a liquid target material that has a width that matches the desired laser spot size (28) for good conversion efficiency and a thickness that matches the laser beam/target interaction depth. The EUV source (12) includes a reservoir (10) containing a pressurized cryogenic liquid target material, such as liquid Xenon. The reservoir (10) also includes an array (14) of closely spaced orifices (16). The liquid target material is forced through the orifices (16) into a vacuum chamber as separated liquid stream filaments (20) of the target material that define the sheet (36). The liquid streams freeze to form an array of frozen target filaments (20). A laser beam (24) is directed to a target area (28) in the vacuum chamber where it irradiates the stream of filaments (20) to create a plasma (30) that emits EUV radiation (32).

Abstract: A frequency down-converter (18) for a receiver (10) in a wireless telecommunications system. The down-converter (18) is capable of simultaneously processing a plurality of signal channels without increased signal distortion over a relatively wide bandwidth. The frequency down-converter (18) employs a suitable mixer (28), bandpass filter (32), attenuator (34) and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband width. In one embodiment, the bandpass filter passes a frequency band at 25 MHz or above. The frequency down-converter (18) generates the IF signal in a single step down-conversion process, or generates the IF signal and then a baseband signal in a two step down-conversion process.

Abstract: A data structure according to the invention is created in memory of a computer for storing data objects for access by a computer application that is executed by the computer. Each of the data objects is associated with a key. The data structure includes a root node object. Additional node objects are added to the root node object based on the characters in the key. The depth of the data structure is equal to the number of characters in the keys. The data structure is ideally suited for efficiently sorting the data objects.

Abstract: A downlink scheduler (20) is provided for scheduling the downlink transmission of data cells in a spot beam processing satellite (12). The downlink scheduler (20) includes a beam selector (48) for selecting one of the spot beams associated with the satellite (12), a plurality of wholesale selectors (50) for selecting one of a plurality of wholesalers, such that each of the wholesale selectors (50) is associated with one of the spot beams, and a plurality of retail selectors (52) for selecting one of a plurality of retail connections, such that each of the retail selectors (52) is associated with one of the wholesalers. Each of the selectors may use a packet fair queuing (PFQ) method to make its selection. The downlink scheduler (20) then passes at least one data cell from a selected retail connection to a downlink modulator (24), thereby scheduling the downlink transmission of data cells in the satellite.