Abstract: A loop filter circuit in a phase lock loop, which also includes a phase detector, a charge pump, and a voltage controlled oscillator (VCO). The loop filter circuit is comprised of two active filters and a common mode feedback control differential comparator (CMFCDC). The active filters process differential signals from the charge pump and output a pair of differential signals to the VCO. The CMFCDC provides a common mode feedback path to both active filters. The loop filter circuit eliminates common mode noise introduced by power supply and ground, and reduces phase jitter in the overall PLL circuits. Each of the active filters is comprised of two independent sets of passive elements that dictate the values of natural modes (poles) and transmission zeros (zeros) of the filtering modules. This allows PLL designers wider latitude in adjusting the unity gain bandwidth of the active loop filter, which contributes to a more stable and better performing PLL circuit.

Abstract: A method of forming an integrated circuit at the wafer level. The integrated circuit package occupies a minimum amount of space on an end-use printed circuit board. A pre-fabricated interposer substrate, made of metal circuitry and a dielectric base, has a plurality of metallized openings which are aligned with metallized wirebond pads on the top surface of a silicon wafer. Solder, or conductive adhesive, is deposited through the metallized openings to form the electrical connection between the circuitry on the interposer layer and the circuitry on the wafer. Solder balls are then placed on the metal pad openings on the interposer substrate and are reflowed to form a wafer-level BGA structure. The wafer-level BGA structure is then cut into individual BGA chip packages.

Abstract: A reference cell for use in a high speed sensing circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistors having its control gate broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via is used to connect the first part to the second part.

Abstract: A semiconductor circuit arrangement providing enhanced security has a first circuitry portion (12) on a semiconductor wafer (10), a second circuitry portion (16) on the wafer separate from the first circuitry portion, the second circuitry portion being coupled (26) to the first circuitry portion and containing access circuitry for allowing access to thereto, and the second circuitry portion being disposed on the wafer such that it can be destructively removed therefrom to leave the first portion of semiconductor circuitry inaccessible through the second portion of semiconductor circuitry. Isolation circuitry (30) is provided for electrically isolating the first circuitry portion following destructive removal of the second circuitry portion.

Abstract: A non-volatile memory device having a main memory that operates synchronously with the system clock and an asynchronous boot block. The boot block can be activated to operate asynchronously upon initial power up or can be switched from synchronous to asynchronous mode upon receipt of a command signal by control logic circuitry within the device.

Abstract: An integrated circuit package that is formed at the wafer level. The integrated circuit package occupies a minimum amount of space on an end-use printed circuit board. A pre-fabricated interposer substrate, made of metal circuitry and a dielectric base, has a plurality of metallized openings which are aligned with metallized wirebond pads on the top surface of a silicon wafer. Solder, or conductive adhesive, is deposited through the metallized openings to form the electrical connection between the circuitry on the interposer layer and the circuitry on the wafer. Solder balls are then placed on the metal pad openings on the interposer substrate and are reflowed to form a wafer-level BGA structure. The wafer-level BGA structure is then cut into individual BGA chip packages.

Abstract: A diual-die integrated circuit package having two integrated circuit chips “flip chip” attached to each other and with one of the chips being aligned at a specified angle in relation to the other chip to allow access to bonding pads on the surface of each chip for wirebonding connection into the chip package. In a first embodiment, the two chips are rectangular in shape and are aligned at an angle of 90 degrees with respect to each other, thus allowing the end portions of the bottom chip to be accessible for connection into the chip package. Other embodiments maintain the chips at angles of less than 90 degrees, such that corner portions of each chip are accessible for connection into the chip package. The invention allows two identically constructed chips to be used for doubling or even greater multiplication of the functionality or memory of the IC package, while still using the same package footprint as for a single chip.

Abstract: A method of communicating with a plurality of contactless data carriers and a contactless data carrier for use in communicating with a base station. The method of communicating includes the base station transmitting a wake up signal for a plurality of contactless data carriers which are in a wait state. Then, the data carriers exit the wait state and transmit identity information to the base station in a time slot that is randomly self-assigned. The base station registers the identity information by polling the registered data carriers and initiates dialogue with registered data carriers in an order determined by the randomly self-assigned time slots of the registered data carriers. The method of communication helps to avoid the problem of data collision that often occurs when multiple contactless data carriers or smart cards operate in the field of a single base station or card reader.

Abstract: A wafer level packaging method which produces a stacked dual/multiple die integrated circuit package. In the method, the wafer with the smaller sized dice of two wafers is processed through a metal redistribution process and then solder balls are attached. The wafer is then sawed into individual die size ball-grid array packages. On the wafer with the larger sized dice, a die attached adhesive material is deposited on the front of each die site location that is intended for the attachment of one of the die-sized BGA packages. The back side of the BGA die package is placed onto the adhesive material and is cured. A wirebonding operation connects the signals from the die-size BGA package to the circuits of the bottom die. A coating material, such as epoxy, is disposed on the wafer to cover the wirebond leads and the assembly is then cured. Then, the stacked-die wafer is singulated into individual stacked-die IC packages.

Abstract: A voltage regulator circuit that receives an input signal and provides an output signal that is clamped at a specified voltage desired for an internal circuit. The disclosed voltage regulator circuit includes a plurality of subcircuits including a voltage tracking subcircuit in which the output voltage tracks the input voltage with no voltage drop when the input voltage starts to rise from zero volts. If the input voltage increases to a desired voltage level for the internal circuit, the voltage tracking subcircuit clamps the output voltage to remain at that voltage. If the input voltage further increases to a higher voltage, the voltage tracking subcircuit is disabled and one of a plurality of voltage maintaining subcircuit takes control so that the output voltage remains at the desired voltage for the internal circuit.

Abstract: A method of depositing an interlevel dielectric material on a semiconductor wafer at a selected thickness such that the best global planarity of the dielectric layer is achieved. A model for the deposition of a silicon dioxide layer is developed based upon the physics of deposition and sputtering and based upon the minimum geometry of features in the semiconductor device. First the geometric parameters of the metal features are determined. Then, based upon the most aggressive aspect ratio between metal lines, the deposition rate to sputter rate ratio is calculated. The film thickness for optimum global planarity is determined based on the calculated ratio. The dielectric material is then deposited on the metal features using HDP-CVD techniques in a manner using the calculated ratio to stop deposition at the determined film thickness such that the optimum thickness for global planarity is achieved.

Abstract: A circuit for parametric testing of I/O's including bidirectionals includes logic which ties the I/O's into a single test chain. A pulse is applied moved down the chain to test the switching levels of the input buffers and the output buffers. The circuit features the ability to program the bidirectionals as either inputs (test mode 1) or outputs (test mode 2) and so allows for its input and output buffers to be tested. The test mode can be selected simply by writing to an externally accessed data register.

Abstract: A quadrature amplitude modulation type demodulator having a dual bit error rate estimator unit that allows for high bit error rate measurements. The dual bit error rate estimator circuit uses information pertaining to the number of corrected bytes from a forward error correction decoder and the count of recognizable patterns of the frame over a sufficiently large number of frames. The two pieces of information can be compared at the bit error rate levels, where both the pattern recognition counter and the FEC decoder are able to output valid data. A comparison between the two pieces of information provides a way to detect the type of noise which occurs on the network and makes it easier to correct problems in signal transmission.

Abstract: A QAM demodulator having a carrier recovery circuit that includes a phase estimation circuit and an additive noise estimation circuit which produces an estimation of the residual phase noise and additive noise viewed by the QAM demodulator. The phase noise estimation is based on the least mean square error between the QAM symbol decided by a symbol decision circuit and the received QAM symbol. The additive noise estimation is based on the same error as in the phase noise estimation, except that it is based only on QAM symbols having the minimum amplitude on the I and Q coordinates. The additive noise estimation is not dependent on the phase of the signal, thus, is independent of the phase noise estimator.

Abstract: A quadrature amplitude modulation (QAM) type demodulator having a pair of direct digital synthesizer (DDS) circuits. The first DDS circuit is located in a baseband conversion circuit before a receive filter and digitally tunes the signal within the receive filter bandwidth. The second DDS circuit is within a carrier recovery circuit located after the receive filter and serves to fine tune the signal phase.

Abstract: In an IC packaging scheme, a multilayer substrate is composed of electrically conductive layers of interconnects, separated by insulative layers of epoxy resin or ceramic and connected by vias. Passive elements are integrated within the substrate at the definition stage during layout of the interconnects. The passives can be used to enhance the electrical performance of the active circuit die to a maximum extent allowed by the material technology used for the substrate. Material selection for the package is made to allow for the best passive integration for a given circuit design. Typical applications include power supply bypass capacitors, radio frequency tuning, and impedance matching. The incorporation of passives in the packaging substrate creates a new class of electrically tailorable packaging that can derive improved performance for any given die design over existing approaches.

Abstract: A mixed signal IC comprising analog circuitry for converting between analog and digital signals and digital circuitry includes circuitry to produce a conversion enable signal which causes the analog circuit to perform a conversion between an analog signal and a digital signal. The circuitry also asserts a warning signal prior to production of the enable signal to momentarily disable the digital circuitry during operation of the analog circuitry. By so doing, noise artifacts from operation of the digital circuitry is eliminated when the analog circuitry is making a conversion.

Abstract: A leadless array integrated circuit package that uses a standard surface mount footprint, but allows use of larger silicon die. The leadless array package mounts to the end user's printed circuit board by solder flow contacts on the perimeter of the chip package that melds with solder paste applied to the printed circuit board and heated in a furnace during package fabrication. The IC chip is laid on a substrate made of a printed circuit board material to reduce thermal mismatches between the leadless array package and the end user's printed circuit board.

Abstract: A QAM demodulator having a first automatic gain control circuit which outputs a first signal that is a function of the received signal, the first signal being used to control the gain of an amplifier which supplies the input of an A/D converter, and a second automatic gain controller which outputs a second signal derived from the QAM circuit after filtering, the second signal controlling the gain of a digital multiplier which produces a signal which feeds into a equalizer by way of a receive filter. The dual automatic gain control circuits, situated before and after the receive filters, allow for better resistance to non-linearity caused by signals in adjacent channels. Additionally, the dual automatic gain control circuits allow for the amplification level of the signal to be limited before the demodulator to eliminate signal distortion and to be set to the correct level internally with digital gain. Also, there is no saturation of the A/D converter since there is no QAM feedback to analog circuits.