Abstract: Memory circuit and a tracking circuit thereof. The tracking circuit includes a dummy bit line (DBL). The tracking circuit further includes a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal. The wordline activation signal causes activation of a memory cell. The tracking circuit also includes a second circuit which is responsive to discharge of the dummy bit line to enable access to the memory cell.

Abstract: Methods and apparatus for canceling distortion in full-duplex transceivers are disclosed. Some example methods to reduce distortion in a full-duplex transceiver include generating a first digital signal, generating a first analog signal based on the first digital signal for transmission over a full-duplex channel, receiving a second analog signal via the full-duplex channel, and generating a second digital signal based on the second analog signal, wherein the second digital signal includes coupling distortion based on the first analog signal. The example methods further include generating an adaptive filter signal based on the first digital signal, and reducing the coupling distortion from the second digital signal by subtracting the adaptive filter signal from the second digital signal.

Abstract: A low-power receiver front-end includes a transconductance amplifier that produces a single-ended current signal in response to a single-ended voltage signal. An output of the transconductance amplifier is provided to an LC tuned circuit. At resonance, the LC tuned circuit generates a differential current signal in response to the single-ended current signal. Single-ended current signals corresponding to the resonant frequency of the LC tuned circuit are converted into differential signals. Further, the LC tuned circuit amplifies the differential current signals by an associated quality factor. Further, a mixer is coupled to an output of the LC tuned circuit. The mixer generates IF signals in response to the differential current signals.

Abstract: A method of designing a semiconductor device includes preparing a first design for a semiconductor device and estimating leakage current for the first design. The method also includes determining a leakage current cumulative distribution function (CDF) for the first design. The method further includes preparing a second design for the semiconductor device based on determination of the leakage current CDF for the first design. Further, the method includes estimating leakage current for the second design. The method also includes determining a leakage current CDF for the second design in accordance to the determination of the leakage current CDF for the first design. Moreover, the method includes selecting one of the first design and the second design based on a comparison of the leakage current CDF for the first design and the leakage CDF for the second design.

Abstract: A wireless transmit/receive unit (WTRU) (152) in a wireless communications system includes a transceiver (153) for transmitting and receiving data from a plurality of base stations (154, 156, 357) and a controller (151) communicatively coupled to the transceiver (153) and configured to adjust an operation mode of the transceiver (153). In the WTRU (152), adjusting comprises configuring the transceiver (153) to begin a radio link handover procedure responsive to receiving a handover (HO) command from a first of the plurality of base stations (154, 156, 357) over a first communications link, specifying a first time, and reconfiguring the transceiver (153) to begin a radio link interruption procedure responsive to an expiry of the first time prior to completion of the radio link handover procedure. In the WTRU (152), the radio link interruption procedure first attempts to re-establish the first communications link.

Abstract: A device is provided for dividing a clock signal by even and odd integers. The device includes a divider, a delay portion and a duty cycle corrector. The divider is arranged to receive the clock signal and can divide the clock signal and output a divided clock signal. The delay portion can output a delayed signal based on the divided clock signal. The duty cycle corrector can output a first signal based on the delayed signal and the divided clock signal.

Abstract: The method, system, and apparatus of a shared error resiliency path through coefficient reordering is disclosed. In on embodiment, determining that an input data is data-partitioned, performing a discrete cosine transform and a quantization of the input data to form a quantized data, separating a first coefficient representing a DC coefficient of the quantized data for each block of the input data, rearranging other coefficients representing AC coefficients of the quantized data for each block of the input data in a fashion produces a zig-zag scan output similar to that of a non-data-partitioned data, bypassing a DC encoding module, determining whether any of the rearranged AC coefficients of the quantized data need to be encoded, performing a zig-zag scan on the rearranged AC coefficients of the quantized data when they need to be encoded, and encoding the rearranged AC coefficients of the quantized data based on the zig-zag scan.

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Abstract: A delay locked loop (DLL) with delay programmability includes a pair of delay blocks, each containing multiple delay elements, but configurable to connect a desired subset of the delay elements between input and output nodes of the respective delay blocks. The subsets of the delay elements in the two delay blocks are connected in series. The ratio of the number of delay elements programmed to form each of the two subsets determines a delay provided as an output by the DLL. In operation, a phase discriminator and a loop filter in combination with the programmed subsets in the delay blocks, operate to generate an analog error signal to compensate for process, temperature and voltage (PTV) variations in the delay provided as an output by the DLL.

Abstract: In an embodiment, the invention provides a method for programming flash memory while maintaining a constant error correction term. A data field and forcing bits are arranged in a packing order. Next, all the forcing bits are set to a logical zero value. A first error correction term is generated using the data field and forcing bits as an input to an ECC encoding algorithm. An exclusive OR function is performed on the constant error correction term and the first error correction term creating a difference term. A forcing function is applied to the difference term creating a new value for the forcing bits. The data field and the forcing bits are written to the flash memory.

Abstract: Transmission of information in a wireless network is performed by allocating a channel from a transmitter to a receiver. The channel has at least one time slot with each time slot having a plurality of symbols. Each slot contains at least one reference symbol (RS). As information becomes available for transmission, it is classified as prioritized information (PI) and other information. One or more priority symbols are generated using the digital samples of the priority information. Other symbols are generated using the other data. Priority symbols are transmitted on the channel in a manner that separation of priority symbol(s) and a reference symbol does not exceed a time duration of one symbol. For example, Rank Indicator (RI) is transmitted using symbol k, ACKNAK is transmitted using symbol k+1; and the reference signal (RS) is transmitted using symbol k+2, wherein symbols k, k+1, and k+2 are consecutive in time. The other symbols are transmitted in available locations.

Abstract: Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess current flowing in a single direction in each metal path is determined. A desired reliability measure for electromigration (EM) is apportioned among the metal paths based on computed parameter values for the corresponding metal path. A reliability analysis for the circuit is performed based on the apportioning. In an embodiment, metal paths which predominantly carry currents with an average value less than a threshold are excluded from being considered as contributors to EM degradation.

Abstract: An amplifier has first and second differential outputs connected to first and second ends of one side of a balun. A second side of the balun, inductively coupled to the first side of the balun, has a center tap that is electrically coupled to a conductive path to a power supply reference node for the amplifier.

Abstract: An integrated circuit (IC) includes a functional circuit and a capacitor cell. The functional circuit may operate with one of two power supply voltages. The capacitor cell is used to provide power supply decoupling for the functional circuit, and includes multiple capacitors, each designed to withstand a maximum voltage equal to the lower of the two power supply voltages. When the functional circuit is to operate with the higher of the two power supply voltages, the capacitors in the capacitor cell are coupled in a series arrangement between power supply and ground terminals of the IC. When the functional circuit is to operate with the lower of the two power supply voltages, the capacitors in the capacitor cell are coupled in a parallel arrangement between the power supply and ground terminals. In an embodiment, the functional circuit is an input-output (I/O) circuit powered by 1.8V or 3.3V power supplies.

Abstract: A system comprises a plurality of requesting agents and granting agents configured in an array of rows and a plurality of columns. Corresponding to each requesting agent is a plurality of row address decoders and column address decoders, one row decoder for each row of granting agents and one column decoder for each column of granting agents. Each row decoder receives a first subset of an address' bits from a requesting agent and generates a row output bit provided to each granting agent in the row of that row address decoder. Each column decoder receives a second subset of bits of the address and generates a column output bit provided to each granting agent in the column corresponding to such column decoder. Each granting agent logically combines the row and column output bits from row and column decoders of a requesting agent to generate a request signal for the granting agent.

Abstract: A design approach provided according to an aspect of the present invention consolidates the constraint files of respective modes into consolidated information and performs place-and-route using such consolidated information. The resource requirements may be reduced as result. Another aspect of the present invention provides a programmatic approach to consolidating timing constraint files of different timing modes into consolidated information.

Abstract: At least some embodiments include a LED driver system. The system includes multiple branches of series-coupled LEDs, multiple current sources, and control logic. Each of the current sources is coupled to a separate branch of series-coupled LEDs. The control logic is coupled to the current sources, and is configured to regulate current through each branch based at least in part on a feedback voltage measured at a node in one of the branches.

Abstract: A receiver with selective sign inversion which can compensate for cross-over conversion is described. Some inputs may be a differential data inputs; a sign select input; a converter having inputs coupled to the differential data inputs and having first and second outputs, wherein the converter is adapted to convert a differential data signal received at the differential data input into a digital data output at the first output and a sign signal at the second output; and a selective sign inverter having a first input coupled to the sign output of the analogue-to-digital converter, a second input coupled to the sign select input and an output, wherein the signal received at the first input of the selective sign inverter is selectively inverted in dependence on the signal received at the second input in order to provide the modified sign select signal.

Abstract: A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.

Abstract: A signal converting system is described that has a multi-segment digital to analog converter coupled to one or more error shaping loops. Each error shaping loop includes a quantizer with a feedback loop configured to generate a control signal responsive to a stream of symbols and to an error signal. Each error shaping loop also includes an inter-symbol-interference (ISI) shaping loop coupled to receive the control signal and to produce an ISI portion of the error signal that is responsive to inter-symbol transition rate.