Abstract: A joint is formed between adjacent edges of a pair of weldable components by forming an undercut on one of the edges. The other edge abuts the undercut so that a portion of the one edge overlaps the other. The edges are laser welded by impinging a beam on the portion to melt the overlap.
Type:
Grant
Filed:
July 17, 1998
Date of Patent:
May 9, 2000
Inventors:
Wido Westbroek, Gursharan Ubhi, David Hughes
Abstract: A regulator circuit is provided for use with cell plate voltage generators of memory cell capacitors and precharge bit lines voltage generators in semiconductor memories. The circuit employs a current source coupled to the charging reference voltage whose output is controlled by a level detector, which receives as input a reference level signal and the cell plate voltage. When the cell plate voltage drops below the reference level, the level detector triggers the current source, thereby recovering the cell plate voltage to the reference level. The level detector can be disabled through an input.
Type:
Grant
Filed:
June 18, 1998
Date of Patent:
May 2, 2000
Assignee:
Mosaid Technologies Incorporated
Inventors:
Ki-Jun Lee, Gurpreet Bhullar, Michael B. Vladescu
Abstract: A compact microwave oven is provided which has a top-opening, space-efficient housing. An optional container is also provided which is adapted to fit within the housing and to contain the foodstuff to be heated.
Abstract: A controller for controlling the pump unit of an oil well includes a sensor having a first and second probe for placement in the flow of oil from the well bore. Each of the probes contains a heater. A constant power source is selectively connected to one of the heaters. Each of the probes also include a linear RTD at each of their tips respectively for generating a signal indicative of the temperature measured at each of the first and second probes. A control unit receives signals from the RTD's and determines a flow rate therefrom. A pump control signal is generated in response to the flow rate, wherein pump control signal continuously varies a predetermined parameter of a pumping unit during operation of the pumping unit.
Abstract: This invention describes a column redundancy method and apparatus in a DRAM that minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required in repairing faulty columns. The invention discloses a DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for energizing appropriate memory columns in response to the decoder memory addresses received at an input thereof; redundant column drivers; and switch means for steering the decoded memory address onto one of either normal or redundant column driver paths. The invention further illustrates a fusing system which minimizes the capacitance of redundant select lines, thereby removing unnecessary delay in the redundant column path.
Abstract: The present invention provides a system and process for correlating points on a spatial body to corresponding points on a data-base body formed from pre-acquired images of the spatial body. The system and process involves matching the spatial points with the corresponding data-base points using relative positional information between the spatial points and the data-base points. Symmetric false matches are detected and discarded by fitting the spatial points and data-base points to a first and second closed body, respectively, and comparing the orientation of the spatial points and the data-base points projected onto the closed bodies.
Abstract: A high voltage generating circuit which provides a constant V.sub.PP output without any threshold voltage drop and which does not suffer from latch-up problems is described. Thus a voltage boosting circuit which provides for a boosted voltage V.sub.PP at an output node, from a supply voltage V.sub.DD, includes a precharge transistor element responsive to a precharge clock signal for transferring the supply voltage V.sub.DD to a boost node for precharging the boost node to the full supply voltage V.sub.DD. The circuit further includes a capacitive element connected between the boost node and a pump node, the capacitive element pumping the boost node in response to a pump voltage signal applied to the pump node; and a switching element connected between the boost node and the output node, for transferring charge from the capacitive element to the output node to provide the boosted voltage V.sub.PP. In particular the precharge transistor element is an PMOS transistor.
Abstract: This invention provides a data bit redundancy method and apparatus that permits the replacement of faulty bitlines on a data bit basis as opposed to a column address basis. This invention provides a semiconductor memory device having memory cells arranged in columns and rows. Normal local data lines are connected to a global data line via a first switch. A redundant memory data line is connected to the global data line via a second switch. A control generating first and second control signals are coupled to the respective first and second switches for operating the switch in response to a status of a fuse component, whereby when the fuse is intact the normal data lines are connected to the global data line and when the fuse is blown the redundant data lines are connected to the global data line, thus not requiring additional redundancy address decoding circuitry.
Type:
Grant
Filed:
December 30, 1997
Date of Patent:
March 2, 1999
Assignee:
Mosaid Technologies Incorporated
Inventors:
John K. Wu, Arun Achyuthan, Guillaume Valcourt
Abstract: This invention describes an addressing and data access method and apparatus which can make use of maximum sized, binary configured blocks of memory or macro cells. The binary sized blocks of memory may be used to implement a non-binary sized overall memory circuit. The apparatus as described makes efficient use of silicon area by combining an optimized number of memory blocks or macro cells having at least two data port per macro cell to implement a non-binary sized memory circuit.
Abstract: A scissor lift has a pair of leg assemblies pivotally connected to a base. Relative movement between the legs and the base is opposed by spring assemblies that may be selectively connected to a carriage to vary the bias on the legs. A cam member secured to the leg acts on the carriage to modify the motion between the leg and the carriage to maintain a uniform vertical spring rate.
Type:
Grant
Filed:
June 20, 1995
Date of Patent:
March 3, 1998
Assignee:
Pentalift Equipment Corporation
Inventors:
Richard T. Rowan, Leonard G. Sutherland, Gary Cooke, Paul A. Pedersen
Abstract: This invention relates to a device to compact parts with an undercut out of powder metal, including a pair of dies linearly moveable relative to one another and then phased, and an associated linearly displaceable pair of punches to produce said parts with said undercut.
Type:
Grant
Filed:
September 11, 1995
Date of Patent:
December 16, 1997
Assignee:
Stackpole Limited
Inventors:
Gerd Hinzmann, Mark Haiko, Frank Ma, Allan Wilson, Keith Buckley-Golder, Robert Round