Abstract: A computer system includes a main processor and a supervisory processor. The main processor provides status signals when a fault condition exists and responds to control signals for fault recovery. The supervisory processor instantiates objects from a fault class in response to the status signals. Objects are polymorphic in that each object has substantially the same methods available at its interface though each object corresponds to a different fault. Methods accomplish fault recovery by providing the control signals. System operation exhibits fewer errors by the supervisory processor and system expansion is more easily accommodated with greater reuse of proven program code than possible with prior supervisory processor software.
Abstract: A reconfigurable computer system which includes two computer subsystems, corresponding lines of the system busses of the two computer subsystems being interconnected by solid state switches. Each of the computer subsystems includes a control component, a service processor, which when an error is detected that would render the subsystem inoperative, causes the solid state switches to open to sever the connection between the system busses of the two computer subsystems so that the computer subsystem that has not suffered such a failure can continue to operate. A communication link is also established between the two service processors. Either, or both, service processors can sever the link between them.
Type:
Grant
Filed:
March 18, 1997
Date of Patent:
April 14, 1998
Assignee:
Bull HN Information Systems Inc.
Inventors:
Leonard Rabins, David A. Bowman, David W. Selway, Clark D. McCaslin, Donald R. Kesner
Abstract: A data processing system includes the functionality of a commercial instruction processor, a scientific instruction processor and a basic instruction processor integrated into a single semiconductor logic element.
Type:
Grant
Filed:
December 7, 1987
Date of Patent:
July 17, 1990
Assignee:
Honeywell Bull, Inc.
Inventors:
Thomas F. Joyce, Richard P. Kelly, Jian-Kuo Shen, Michel M. Raguin
Abstract: A multifunction arithmetic indicator that is associated with and controlled by an arithmetic logic unit (ALU) to store standard arithmetic indicator information such as overflow, carry, arithmetic sign and all bits equal zero that are generated by the ALU when processing binary information. A control unit sends control signals to multiplexers in the multifunction arithmetic indicator that cause the selection of appropriate arithmetic indicator information from the ALU, no matter what the bit length of binary words being processed by the ALU. The selected indicator information is stored in a register for later use.
Abstract: An electronic assembly is made up of a number of electronic components. Each of the electronic components having a means for putting the component in a quiescent state while the remaining components are in a functional state, thereby enabling the testing of individual components without disassembly.
Abstract: A computer system includes a first processor with main memory, an input/output processor with associated memory and an archival memory. Prior to reloading a new operating system from archival memory into the main memory, information such as timer information is stored in the input/output memory. The input/output memory continues to update the timer information until the second operating system is bootstrap loaded into the main memory. The timer and other information may then be returned to the first processor and main memory for use by the second operating system.
Type:
Grant
Filed:
September 21, 1987
Date of Patent:
January 17, 1989
Assignee:
Honeywell Bull Inc.
Inventors:
Gary J. Goss, Thomas S. Hirsch, Thomas O. Holtey