Abstract: A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connetion between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.
Type:
Grant
Filed:
May 16, 1991
Date of Patent:
July 7, 1992
Assignee:
AT&T Bell Laboratories
Inventors:
Kuo-Hua Lee, William J. Nagy, Janmye Sung