Abstract: A method to achieve good stepper focus and exposure over an entire wafer for a particular mask level before the start of a product run is described. This method can also be used to produce a characterization of lens field curvature (i.e., a surface of optimum focus across the lens) and to characterize lens astigmatism, defocus sensitivity, relative resolution, and other characteristics, and to check the stepper for optical column tilt. The process prevents the complexities of resist development from affecting determination of focus. The process involves forming an array of latent images in a resist and examining the scattered light from the edges of the latent images. Analysis of the scattered light quickly provides information on correct exposure and focus together with lens characteristics over the printing field.

Abstract: A method for forming tungsten plugs and layers is disclosed. A thin layer of polysilicon or amorphous silicon is formed within a contact opening. The silicon is exposed to WF6, thereby forming a tungsten plug.

Abstract: An improved method of integrated circuit fabrication is described with a photolithographic step involving pattern decomposition. A desired final pattern is decomposed into two or more component patterns for photoresist imaging, leading to improvements in image fidelity.

Abstract: An integrated circuit and its method of formation are disclosed. The circuit utilizes a spin-on glass as an interlevel dielectric. Above and below the spin-on glass is located a phosphorous doped dielectric. The doped dielectric prevents sodium from becoming mobile under the influence of subsequently applied electric fields.

Abstract: Microwave radiation, perhaps with microwave absorbing materials, is utilized to provide heating of partially formed integrated circuits in a variety of circumstances.

Abstract: Undesirable birds beak pull back due to ion implant damage is alleviated by additional oxide growth.

Abstract: A twin tub integrated circuit and method for its formation are disclosed. A portion of the substrate is covered by photoresist while an n region is formed, illustratively, by ion implantation. Then the n region is covered with a protective material, illustratively a spin on glass or another photoresist. The previously-formed photoresist is removed and a p-type implant is performed to create an p region. When all the protective layers are removed, both regions have upper surfaces which are co-planar. The co-planar surfaces, a departure from previous practice, make submicron lithography easier. The regions are annealed to form twin tubs.

Abstract: A variety of test structures may be fabricated with aluminum runners and overlying dielectrics. The dielectrics are removed and bumps are observed upon the aluminum runners. Unevenness in the bump distribution is a predictor of long term reliability problems. A test structure may be utilized to design integrated mass production fabrication processes.

Abstract: A method to achieve good stepper focus and exposure over an entire wafer for a particular mask level before the start of a product run is described. This method can also be used to produce a characterization of lens field curvature (i.e., a surface of optimum focus across the lens) and to characterize lens astigmatism, defocus sensitivity, relative resolution, and other characteristics, and to check the stepper for optical column tilt. The process prevents the complexities of resist development from affecting determination of focus. The process involves forming an array of latent images in a resist and examining the scattered light from the edges of the latent images. Analysis of the scattered light quickly provides information on correct exposure and focus together with lens characteristics over the printing field.

Abstract: A method and apparatus for the manufacture of integrated circuits including the placement of a single tube for introduction of dopant gases into a process chamber is disclosed.

Abstract: A method of semiconductor fabrication which permits the creation of openings which have dimensions smaller than what may be achieved by conventional lithography. In an illustrative processing sequence, a pattern transfer material is deposited upon another material layer. The pattern transfer material is covered with photoresist which is subsequently patterned. With the patterned photoresist as a mask, the pattern transfer material is etched with a process which creates inward sloping walls. Then the pattern transfer material is used as a mask to etch the underlying material. The inward sloping walls of the pattern transfer material permit creation of an opening in the underlying material which is smaller than the corresponding opening in the photoresist. The method may also be used to create trenches or field oxides which have dimensions smaller than those achievable by lithography.

Abstract: An apparatus for the convenient viewing of scribed numbers upon selected wafers is disclosed. The apparatus supports a wafer cassette and raises predetermined wafers and illuminates the identification numbers scribed thereon.

Abstract: A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an anti-reflective coating to prevent rainbowing or spiking of the coating into the underlying metal.

Abstract: A method of forming electromigration resistant integrated circuit runners is disclosed. A collimated beam of particles is directed toward a substrate to form a metal nucleating layer. Then a non-collimated beam is used to form the rest of the metal layer. Then the layers are patterned to form runners.

Abstract: Linewidth control features having integral transistors are disclosed. Optical and electrical measurements of the linewidth control feature and its associated transistor may be correlated thereby providing a method of improving production processes.

Abstract: Cleaning of a micromimiature high-density flip-chip assembly is carried out by spinning the assembly while applying cleaning fluid to a central portion of the assembly. Confinement of the cleaning fluid to a critical interconnection space of the assembly is ensured by a centrally apertured cover that resiliently engages the top of the assembly. During spinning, cleaning fluid is introduced through the aperture in the cover and is directed into and confined to flow radially in the interconnection space.

Abstract: Sub-micron PMOSFETs including n.sup.+ polysilicon gates and buried channels having impurity concentrations comprising indium or gallium are provided. The buried channel PMOSFETs have improved short channel characteristics and are particularly suitable for use in CMOS technologies.

Abstract: A process for forming isolated active device regions on a silicon substrate comprises the steps of forming at least one trench in a silicon substrate to define at least two active device regions on the substrate to be isolated from each other, depositing an electrically insulative material on the substrate to fill the trench with the material, planarizing the surface of the substrate, performing a masking and etching operation to expose at least one active device region on the substrate, selectively growing a first epitaxial layer of silicon on the exposed active device region, masking the substrate to leave exposed at least one other active device region on the substrate, selectively growing a second epitaxial layer of silicon on the other exposed active device region, the first epitaxial layer and second epitaxial layer being doped with dopant atoms to the same or different dopant concentration to provide at least two isolated active device regions on the silicon substrate.

Abstract: Active circuitry is placed under the bond pads in an integrated circuit having at least three metal levels. The metal level adjacent the bond pad level acts as a buffer and provides stress relief and prevents leakage currents between the bond pad and underlying circuitry.

Abstract: Analog and mixed signal integrated circuits are tested using the modified Volterra series to model the integrated circuit being tested. An adaptive algorithm, for example, least mean square or Kalman, is used to determine to coefficients of the Volterra series. The coefficients are then used to calculate the THD and SNR.