Abstract: A novel partitioned parity check and regeneration circuit is provided for receiving an input data word which is partitioned and the partitioned bits are stored in a partitioning register to provide a subset input data word of fewer data bits than the input data word. Parity register means including a parity register are associated with the partitioning register to provide a parity check of the partitioned data word and for generating an error detect signal when the data bits in the partitioning register are not properly latched. The parity bits stored in the associated parity register are employed with associated output logic to generate regenerated parity bits associated with the output of the data bits in the partitioning register to preserve the integrity of the data.
Abstract: A multi-function high speed sequencer is provided in a high speed instruction processor. The high speed sequencer comprises a first input latch coupled to logic signals for producing a first sequence signal. A chain of alternately clocked even and odd principal latches are coupled to the output of the first input latch to produce even and odd principal sequence signals for accessing a high speed MSU. A plurality of staging latches are coupled between the odd and the even principal latches for producing even and odd secondary sequence signals for accessing a slower speed MSU.
Type:
Grant
Filed:
September 6, 1989
Date of Patent:
September 3, 1991
Assignee:
Unisys Corporation
Inventors:
Michael Danilenko, David J. Tanglin, Lawrence R. Fontaine
Abstract: Apparatus for checking and detecting erroneous start signals is provided in the arithmetic section of a high speed instruction processor and may be embodied in other types of processors. The novel logic circuits include circuits for detecting an attempted start signal while a previous instruction is still in process; logic circuits for detecting when an even arithmetic sequence and an odd arithmetic sequence other than the first sequence are being concurrently processed; and logic circuits for detecting when an AR start instruction is being attempted during a wrong minor cycle.