Abstract: The multi-mode Multiplier-And-Accumulator of the present invention is used with the double-precision Complex-Valued Multiplier-And Accumulator as a main configuration, and the different precisions and digital modes make it more flexible, compared to the traditional real number Multiplier-And-Accumulator. In addition, it does not have a data alignment problem which occurs in the traditional application of different precision Subword Parallel processors. This kind of Multiplier-And-Accumulator takes a double-precision Complex-Valued Multiplier-And- Accumulator as the main configuration, with four double-precision real-valued multipliers and several groups of accumulators to assist in different modes ofoperation. Each double-precision real- valued multiplier can be segmented into four single-precision multipliers, and then double-precision multiplier products are obtained by means of displacement addition.

Abstract: The present invention relates to a HDMI connector comprising of an insulated housing, a metallic housing and a contact terminal unit. The insulated housing is standardized but the metallic housing and the contact terminal unit are modified and combined with the insulated housing to form the HDMI connector of the present invention. The metallic housing is modified to have a flange or no flange and to have vertical insertion type pins or horizontal SMT type pins, and the terminal contact unit attached thereto. The terminal unit is modified to have spikes whose rear ends are either bent and flattened to form horizontal SMT type terminal solder pins or to have spikes whose rear ends are not bent and not flattened to form vertical insertion type pins.

Abstract: This invention discloses a reduced-width, low-error multiplier that can be used in Digital Signal Processing (DSP). Specifically, this invention relates to a reduced-width, low-error multiplier capable of processing digital signals of communication systems such as a timing recovery circuit, a carrier recovery circuit, and a FIR filter, etc. This invention derives a binary compensation vector to compensate for the error caused by the reduction of area without any hardware overhead, and implements the compensation structure of an Array and a Booth multiplier to reduce hardware complexity.

Abstract: This invention relates to methods for manufacturing super-micro fibers to produce fibers having dimensions of between 0.003-0.0003 denier per filament. The manufacturing methods include the following steps: blending polyamide-polyester mixtures; passing said polyamide-polyester mixtures through single-path and twin-screw extrusion processes; spinning said polyamide-polyester mixtures; melting and dissolving said polyamide-polyester mixtures; and separating polyester compounds from said polyester-polyamide mixtures to form polyamide compound or super-micro fibers.

Abstract: An aerial vehicle speed correlation method for two-dimensional visual reproduction of laser radar images of the present invention is capable of altering and controlling the output timing of the invention's laser radar system rated output lines based on the moving distance and the speed of an aerial vehicle. The speed error correlation method of the present invention is not limited to outputting one output line for every scanned line (N) for reducing the accumulation of geometric distortion error along the in-track direction of the scan frame. The speed correlation method of the present invention uses a set of generated fire table of equation to correct tangential error along the cross-track direction and to improve the reproduction quality of the laser radar images.