Abstract: This invention discloses a reduced-width, low-error multiplier that can be used in Digital Signal Processing (DSP). Specifically, this invention relates to a reduced-width, low-error multiplier capable of processing digital signals of communication systems such as a timing recovery circuit, a carrier recovery circuit, and a FIR filter, etc. This invention derives a binary compensation vector to compensate for the error caused by the reduction of area without any hardware overhead, and implements the compensation structure of an Array and a Booth multiplier to reduce hardware complexity.

Abstract: An aerial vehicle speed correlation method for two-dimensional visual reproduction of laser radar images of the present invention is capable of altering and controlling the output timing of the invention's laser radar system rated output lines based on the moving distance and the speed of an aerial vehicle. The speed error correlation method of the present invention is not limited to outputting one output line for every scanned line (N) for reducing the accumulation of geometric distortion error along the in-track direction of the scan frame. The speed correlation method of the present invention uses a set of generated fire table of equation to correct tangential error along the cross-track direction and to improve the reproduction quality of the laser radar images.