Abstract: I/O lines on a CMOS circuit are precharged to preferred voltage levels in order to avoid latch up. The precharging is achieved by using N channel transistors to provide a precharge which is at a threshold voltage (V.sub.T) below bias voltage V.sub.CC, or (V.sub.CC -V.sub.T). This results in a lower forward bias when V.sub.CC bumps down after the I/O lines are floated. By lowering the precharge voltage by a level corresponding to a threshold voltage (V.sub.T), the allowed range of power supply voltage bumping is increased by this amount. This eliminmates the destructive effect of a negative bump of V.sub.BE, which would have presented a diode forward bias condition. Instead, the power supply may bump to (V.sub.BE +V.sub.T).

Abstract: The present invention constitutes an improvement of the Local Encroachment Reduction (LER) process developed by Tyler Lowrey at Micron Technology, Inc. of Boise, Idaho. LER consists of selectively etching a portion of the field oxide which has encroached into a DRAM cell's active area and then subjecting the cell to a high-energy boron implant to maintain adequate active area isolation. Although the boron implant effectively decreases the width of the depletion region between n+ active areas and p+ substrate, it has the undesirable effect of reducing the breakdown voltage at the n-p junctions in the bird's beak regions at the edges of the active regions, thus increasing the cell's susceptibility to gated-diode breakdown following creation of the cell plate. The present invention solves this problem by creating a graded junction in the bird's beak regions of the cell. The graded junction reduces the electric field intensity in the junction region, resulting in an increase in the breakdown voltage.

Abstract: A dynamic randon access memory (DRAM) is formed in a series of masking steps, during which a first layer of polysilicon is anisotropically etched. After the anisotropic etch, junctions are added to the polysilicon through doping techniques. A second layer of polysilicon is then deposited and is isotropically etched. By the sequence, critical dimensions are established at preliminary mask layers and subsequent layers do not require the high degree of criticality of dimension.

Abstract: A two-piece burn-in board is used in semiconductor testing. The board can be disassembled so that it has ability to act as a device carrier wherein each individual device is completely isolated and as a standard burn-in board wherein all devices share the common signals. This ability to isolate or combine signals makes the board useable for functional device test/characterization and burn-in.

Abstract: A fluctuating voltage to be monitored is fed to the non-inverting input of a first op amp via a first input resistor; a reference voltage is fed to the inverting input of the second op amp via a second input resistor. The inverting input of the first op amp is taken from a first voltage divider connected between the reference voltage and ground; the non-inverting input of the second op amp is taken from a second voltage divider connected between the fluctuating voltage and ground. The power inputs of both op amps are connected to a positive voltage and ground. The output of both op amps is tied together, with a first feedback loop feeding the tied output voltage to the non-inverting input of the first op amp via a first high-resistance gain-setting resistor, and a second feedback loop feeding the tied output voltage to the inverting input of the second op amp via a second high-resistance gain-setting resistor.

Abstract: A method of sealing a ceramic lid on a ceramic semiconductor package with a high-power laser beam. As an aid to package assembly prior to the fusion of the package lid to the package body, a lid recess is created around the die installation cavity of the package body. Following the installation of a die within a package cavity, the package body is retrieved from a process tray by a pick and place robot and placed in a position locating fixture. The same robot then retrieves a ceramic lid from an automatic lid dispensing unit, and places it within the lid recess of the package body. With the lid positioned within the recess, a Yttrium-Aluminum-Garnet (YAG) laser with beam splitter optics is moved by an X-Y table arm precisely over the top of the package. Moving with a linear speed of approximately 2.1 cm/sec. and with a power setting of approximately 170 watts, the split beam YAG laser simultaneously fuses a pair of opposite edges of the lid to the adjacent edges of the recess.

Abstract: A method of manufacturing a series of leadframe strip carriers, the individual members of the series having common external dimensions to facilitate production handling equipment setup and internal slot dimensions which vary to accommodate the various widths of available leadframe strips. This new method of manufacturing leadframe strip carriers results in a much lower unit cost, as compared to carriers manufactured from aluminum extrusions. This has been achieved using an injection molding process employing a single mold which produces constant length, width and height dimensions throughout the series, and which has an internal form die, the position of which can be varied with spacing inserts that can be either removed or transferred to the other side of the mold cavity as the mold is modified for progressively-narrower leadframe strips. To ensure durability, highly-abrasion resistant, fiber-reinforced plastic material is used to create the carriers.

Abstract: A process for simultaneously applying precut protective swatches of precured polymer film to each semiconductor die on a wafer, whereby an indexed greater-than wafer-width strip of precured polyimide film having a heat-attach adhesive on its lower surface is die punched to remove essentially half of the scrap film, material between each of the individual portions on the film which dimensionally correspond to the areas of individual dies on a silicon wafer requiring protection. Each punched area corresponds to areas on the wafer die matrix that are to remain unprotected. Following this first punching, a strip of dimensionally-stable backing paper coated with heat-release adhesive is bonded to the upper surface of the polyimide strip in the region which will become matrices of swatches. The double layer strip is then subjected to second die-punch process which removes the remaining scrap film material between the individual swatches.

Abstract: A pumpdown circuit uses voltage sensing to bring a low node to a potential of V.sub.SS +V.sub.T by first grounding the node and then floating the node to the V.sub.SS +V.sub.T potential. When a sensing node is at the V.sub.SS +V.sub.T potential, the sensing node is maintained at a level above ground by leakage current through a pump-up circuit. Biasing the digit and digit* lines to a potential V.sub.T above ground reduces current (amperage) requirement, because the digit and digit* lines do not have to be discharged completely to ground. The momentary discharge of the sense amp node to ground allows the sense amp to behave like a conventional sense amp during initial sensing, thereby allowing a minimum digit/digit* sensing potential to approximate ground plus V.sub.T.

Abstract: A three port memory device has two serial ports and a random access memory port. The random access memory port is addressed to a random access memory in a conventional manner, using RAS and CAS address signals. Data may also be supplied and retrieved through two serial ports to a pair of serial access memories for transfer between the serial ports and the random access memory. This configuration permits formatted data to be simultaneously assessed through the two serial ports, while the random access memory port is being accessed.

Abstract: During solder-reflow attachment of surface-mount electronic components to a printed circuit board, vibrational energy sufficient to overcome the static coefficient of friction between the leads of a component and their respective connector pads is applied to the board, with the result that the surface tension of the molten solder between the leads and the pads will produce a best-fit alignment of the leads of each component on their corresponding connector pads.

Abstract: A printed circuit board is designed to conform to a single in-line memory module (SIMM) configuration, but includes multiple rows of the memory devices. By controlling a sequence of enable signals, selection of a single row from the multiple row of memory devices can be accomplished. The ability to address the different rows multiplies the memory capacity of the board by the number of rows of memory devices.

Abstract: A decoupling capacitor system for improving the reliability of digital logic circuit boards such as single inline memory modules which use surface-mount decoupling capacitors. The system comprises one or more units of two or more series-connected capacitors connected between the chip supply voltage (Vcc) input and the chip ground (Vss) connection. Given no change in the reliability of the individual capacitors, the reliability of a circuit board can typically be improved by several order of magnitude.

Abstract: A low-profile, folded-plate, dynamic random access memory (DRAM) cell capacitor which can be fabicated with only two photoresist masks using equipment and processes identical to those used for the fabrication of DRAM cells having planar capacitors. The n+ silicon substrate, which is an extension of the cell's field-effect transistor drain, functions as the lower half of the capacitor's storage-node plate. The capacitor's field plate is comprised of a doped polycrystalline silicon-2 (poly-2) layer. The field plate is insulated on its lower surface from the n+ silicon substrate by a first dielectric layer of silicon nitride; it is insulated on its edges with a silicon oxide dielectric and on its upper surface with a second dielectric layer of silicon nitride from the upper half of the storage-node plate, which is comprised of a sandwich of n-type poly-3 and poly-4 layers. The upper half of the storage-node plate is tied to the n+ silicon substrate with a buried contact which is an extension of the poly-4-layer.