Patents Represented by Attorney Jonathan P. Mever
  • Patent number: 5293610
    Abstract: A memory system, having security against unauthorized accessing of the contents of the memory system, comprises a first alterable memory (6), a second non-alterable memory (14, 16) and a data bus (5) for allowing external access to data stored in the memory system during a test mode of operation. The first alterable memory (6) comprises an options register (10) having a security bit (SEC) which, when programmed to an active state, prevents external access to the data stored in the first alterable memory during the test mode. The first alterable memory (6) further comprises a first data memory (8) having at least one security byte (VALSEC) which, when programmed to a predetermined state, prevents external access to the data stored in both the first alterable memory (6) and the second non-alterable memory (14, 16) during the test mode.
    Type: Grant
    Filed: June 10, 1991
    Date of Patent: March 8, 1994
    Assignee: Motorola, Inc.
    Inventor: Roland H. Schwarz