Abstract: Pinnacle concepts are not amenable to detection by the use of keywords. A unit of natural language discourse (UNLD) “refers” to a pinnacle concept “C” when that UNLD uses linguistic expressions in such a way that “C” is regarded as expressed, used or invoked by an ordinary reader of “L.” A reference can have a “reference level” value that is proportional to: the “strength” with which the pinnacle concept is referenced, the probability that a pinnacle concept is referenced or both strength and probability. Pinnacle concepts can be divided into Quantifiers and non-Quantifiers. A Quantifier can modify the reference level assigned to a non-Quantifier. A concept “C,” that is determined to be referenced by a UNLD “x,” after application of its Quantifiers, is said to be asserted by “x.” Concept-based classification is the identification of whether a pinnacle concept “C” is asserted by a UNLD. Concept-based classification can be used for concept-based search.

Abstract: Searching computer-accessible content can be described as the utilization of an automated process to determine occurrences of where a sought-for concept is referred to in natural language discourse. Concept-based search refers to the reliable identification, within computer-accessible content that represents natural language discourse, of instances in which a particular pinnacle concept “C” is referenced. References to pinnacle concepts are not amenable to detection by the use of keywords. For each pinnacle concept “C,” whose reference is to be determined, a set of linguistic features can be compiled that is referred to herein as a “concept feature set.” In general, it is desirable for a concept feature set to be “complete.” A definition of completeness is presented. Concept-based search can be used in conjunction with keyword-based search.

Abstract: Data processing resources are distributively provided to an emulation system to locally and correspondingly configure emulation integrated circuits. In certain embodiments the data processing resources also perform emulation functions. In one embodiment, the distributed data processing resources are disposed on logic boards having emulation ICs that include the reconfigurable logic resources. In another embodiment, data processing resources receive commands transmitted from a workstation executing electronic design automation (EDA) software. In other embodiments, at least some of the distributed data processing resources are disposed on the emulation ICs. The board and IC disposed distributed data processing resources cooperatively perform the configuration and emulation functions as described.

Abstract: Systems and methods for verifying integrated circuit designs: (a) receive input corresponding to physical layouts of cells of the design and available master cells. The systems and methods then determine if the design cells are intended to correspond to one of the master cells, and if so, the systems and methods then determine if the layouts of the cells and the corresponding master cells match one another, e.g., by a layout vs. layout comparison of the design cell with the master cell to determine if the coordinates of the polygon(s) in the design cell match corresponding coordinates of the polygon(s) in the master cell. An “XOR” comparison may be used to determine if the design cell features match the corresponding master cell features. Computer-readable media may be adapted to include computer-executable instructions for performing such methods and operating such systems.

Abstract: The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs a variable rate back channel, incorporated within an existing communication that does not increase or adversely impact the transmission rate of data on the communication channel.

Abstract: System, methods, and apparatus for verifying microcircuit designs by interleaving between random and formal simulation techniques to identify input traces useful for driving designs under test into sequences of device states. In a method aspect the invention provides process for beginning random simulation of a sequence of states of a microcircuit design by inputting a sequence of random input vectors to a design under test model in order to obtain a sequence of random simulation states; monitoring a simulation coverage progress metric to determine a preference for switching from random simulation to formal methods of simulating states in the design under test; beginning formal simulation of states in the design under test and monitoring a formal coverage progress metric to determine a preference for resuming random simulation of states of said microcircuit design; and resuming random simulation.

Abstract: A decomposition technique, for solving combinational constraint expressions, is presented. Decomposing a set of constraints can increase the opportunities for dividing them into independent sets that do not need to be conjoined in a constraint-solving process using a BDD representation. An AND decomposition, relying on a Theorem 1, is presented. An OR decomposition, relying on a corollary of Theorem 1, is presented. Theorem 1 provides an operation to test for, and create, a pair of sub-constraints G and H which are independent in any two variables x0 and x1. A decomposition procedure is presented for separating as many variables as possible, of an input constraint, into disjoint sub-constraints. A merging procedure is presented, that can be used if a decomposition does not only contain constraints whose support sets are disjoint from each other. The decomposition procedure can also be used to identify hold constraints.

Abstract: The present invention accepts an acyclic concurrent control-flow graph (CCFG) and produces a sequential control flow graph (SCFG) that, when executed, behaves functionally like the CCFG would if it were run on concurrent hardware. An SCFG can be easily translated into a traditional sequential programming language such as C or assembly to be executed on a traditional sequential processor. Determining the order in which CCFG nodes will be run is the first step in the process. Control edges in the CCFG constrain the order in which CCFG nodes must run; communication between threads generally impose further constraints. An easy way to further constrain a valid order of CCFG nodes is to augment the CCFG with data dependence edges (representing inter-thread communication) and to then topologically sort the nodes in the augmented graph to produce an ordering.

Abstract: In a finite state machine (FSMverify) a set of goal states, to be searched for their reachability from a start state, is defined. An overapproximated path is found from a start state to a goal state by a forward approximation technique. The overapproximated path representation relies upon a partitioning of the state and input bits of FSMverify. A state matrix of the overapproximated path is organized by time-steps of FSMverify along a first dimension and by partitions of FSMverify state bits along a second dimension. An underapproximated path, along the path of the stepping stone matrix, is determined. Underapproximation is typically accomplished by simulation. A sequence of states to be output is updated with the underapproximated path. If a start to goal state sequence has been found, the procedure ends. Otherwise, the above steps of over and under approximation are repeated, using the results of the last underapproximation as a start state.

Abstract: Relates to automatic conversion of assumption constraints, used in circuit design verification, that model an environment for testing a DUT/DUV, where the assumptions specify sequential behavior. Such assumptions are converted, with the use of logic synthesis tools, into a gate-level representation. For formal verification, a verification output is constructed from the gate-level representation and DUT/DUV assertion-monitoring circuitry. A formal verifier seeks to prove the verification output cannot indicate a design error. For simulation verification, the gate-level representation is converted into a hybrid representation comprising pipelines and combinational constraints. During simulation, the pipelines hold state information necessary for a solution, of the combinational constraints, to be in accord with the sequential assumption constraints. For certain sequential assumption constraints, the combinational constraints are insufficient to insure avoidance of deadend states.

Abstract: A technique for observability based coverage of a design under test (DUT) is presented. A conventional simulation signal is augmented to include a “tag value.” In the course of a simulation, assignment statements (for which observability-based coverage is desired) “inject” tag values on their output signals. A tag value contains an identifier uniquely identifying the assignment statement that produced it. A tag value also contains a “tag history.” The tag history contains copies of the tag values for assignment statements earlier in the flow of control or in the flow of data. If a tag propagated through the DUT appears at an observable output, the circuit designer knows that the assignment statements it identifies have satisfied observability based coverage.

Abstract: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions. The constraint expressions may impose a linear ordering in which random variable values must be assigned and this dependency is expressed by directed acyclic graphs (DAGs). The constraint expressions constraining each random variable are converted into ranges of permissible values from which a value is chosen at random.

Abstract: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. If a constraint block of an instance is active or ON, then all the constraint expressions in the block will act to constrain their lhs random variable.

Abstract: A method and an apparatus for coupling the results of behavioral synthesis with those of logic synthesis. It uses a timing verifier to precalculate the timing characteristics of a circuit for use by behavioral synthesis. Timing for control chaining is included in the precalculated timing characteristics. Once behavioral synthesis is complete, logic synthesis is informed of timing constraints introduced by behavioral synthesis.

Abstract: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. A constraint_expression can constrain any random variable which has been declared at its level in the class hierarchy, or at any higher level.

Abstract: Hardware Verification Languages (HVLs) permit the convenient modeling of the environment for a device under test (DUT). HVLs permit the DUT to be tested by stimulating certain inputs of the DUT and monitoring the resulting states of the DUT. The present invention relates to an HVL, referred to as Vera, for the verification of any form of digital circuit design. Vera is preferably used for testing a DUT modeled in a high-level hardware description language (HLHDL) such as Verilog HDL. More specifically, the present invention relates to an HVL capability, know as an “expect,” for monitoring the values at certain nodes of the DUT at certain times and for determining whether those values are in accordance with the DUT's expected performance.

Abstract: In the design of large scale digital integrated circuits, it is often desirable to formally verify whether an implementation design is equivalent to a reference design. The present invention utilizes a particular type of structural similarity between the reference and implementation designs, which we shall refer to as “structural dependence,” in order to broaden the class of circuits that are formally verifiable in an efficient manner. Structural dependence is the dependence of the higher-order result bits of a design upon the circuitry driving the lower-order result bits. Structural dependence is utilized in partitioning the two circuits, also referred to as &eegr; and &eegr;′, to be compared. Such partitioning creates subcircuits &eegr;i for circuit &eegr; and subcircuits &eegr;′i for circuit &eegr;′. Each subcircuit &eegr;i drives a primary output zi and each subcircuit &eegr;′i drives a primary output z′i.

Abstract: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. Because random variables may also appear on the right-hand-side (rhs) of a constraint expression there is an ordering in which random variable values must be assigned and this dependency is expressed by directed acyclic graphs (DAGs).

Abstract: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the monitoring of a device under test (DUT). The HVL language supports Object-Oriented Programming (or OOP). Within this OOP framework, the present invention provides a monitoring facility comprised of three main stages: i) Coverage Definitions, ii) Coverage Instantiation and Triggering and iii) Coverage Feedback. A coverage definition is very similar to an OOP class definition, but does not contain methods or variables. Instead, the basic purpose of a coverage definition is to declare “monitor bins” in terms of a state variable. Essentially, each monitor bin declaration has a unique bin name which is associated with a particular behavior of the state variable and the unique bin name is used to record the state variable's behavior. Instantiation of a coverage definition produces a coverage instance.

Abstract: Finite state machines (FSMs) are synthesized from hierarchical high-level descriptions and optimized. Partitions of the FSM are selected by scanning the nodes of the hierarchical description and assigning to each suitable node a metric based upon the reachability function of the FSM. The metric is an indicator of the desirability of using the partition of the FSM, corresponding to the node, as a region of the FSM upon which to apply FSM optimization techniques. Based upon the metric, certain partitions are selected for optimization. Optimization of a partition can include the steps of converting the partition to a state graph, state graph minimization and conversion back to an FSM. Any hierarchical high-level language is suitable for the present invention, provided that a correspondence between nodes of the high-level description and partitions of the FSM can be determined.