Abstract: A method for forming an HSG (hemispherical grain) layer on a storage electrode of a capacitor formed on a substrate is provided. The method includes a step of introducing a source gas into a reacting chamber to deposit a small amount of HSG nuclei on a conductive layer pattern of a capacitor electrode during a step of stabilizing the substrate temperature. After the substrate temperature is stabilized, a larger amount of source gas is introduced into the chamber to form additional HSG nuclei. Thereafter, a step of annealing is performed to form the HSG layer.

Abstract: A motion correction device for images recorded by a camcorder from incident light having an incident direction. The device comprises at least one of horizontal and vertical component pick-ups. Each component pick-up comprises a converter for converting light into electrical signals, and a thin transmitter-reflector for transmitting a portion of the incident light at substantially the incident direction and for reflecting a remaining portion of the incident light at a range of other directions such that substantially all the reflected light impinges on the converter. The thin transmitter-reflector may be a curved transmission mirror for focusing the reflected light on the converter or a flat transmitter-reflector with a condenser disposed between the thin transmitter-reflector and the converter for focusing the reflected light onto the converter.

Abstract: A method of fabricating a semiconductor device includes nitriding a native oxide layer on a pattern of polysilicon layers to be used as the lower electrode of a capacitor in LPCVD equipment at a constant temperature in an environment of ammonia gas. A nitride layer is then deposited onto the nitrided native oxide layer in the in-situ state. An oxide layer is then deposited onto the entire nitride layer, and thereafter a pattern of upper electrodes are formed on the oxide layer, thereby shortening the period of time required for forming the entire nitride layer of the NO dielectric layer without any deterioration in the product quality.

Abstract: A first-in, first-out memory circuit includes first and second memory part respectively having first and second address locations each of which has a first word length, a write address counter outputting a write address signal and a memory part selection signal to the first and second memory parts in response to a word length selection signal, and a memory part enable circuit which is coupled between the write address counter and the first and second memory parts and receives the memory part selection signal. The memory circuit also includes a data bus which is applied with the input data and which includes a first data bus having the first word length and a second data bus having the first word length, and a data input part which is coupled between the data bus and the first and second memory parts.

Abstract: A color palette RAM 100 according to the present invention, which is provided with a RAM 101 for storing color information, an address register 102 that holds an input address and outputs an address to the RAM 101 and a comparator circuit 103 that compares the input address and the address output by the address register, outputs a match signal if these addresses match and stops the operation of the RAM 101 based upon the match signal, is capable of minimizing the level of the power consumed for precharge operations and the like, since the RAM can be set in a disabled state when the same address in the color palette RAM is accessed continuously, as is the case, for instance, when pixels of the same color lie adjacent to one another.

Abstract: A rotary vane pumping machine includes a stator and rotor in relative rotation. The rotor has a plurality of radial vanes slots and each one of a corresponding plurality of vanes slides within a radial vane slot of the rotor. Each pair of adjacent vanes defines a vane cell. A rotary scavenging disk is disposed along the stator circumference, and is sized such that the rotary scavenging disk extends into the vane cell. An outer circumferential edge of the rotary scavenging disk is in sealing proximity with an outer circumferential edge of the rotor and recesses within the rotary scavenging disk mesh and seal with the extending and retracting vanes.

Abstract: A liquid short-chain polymer of the general formula RaSi(OH)b or (R)aSiHb(OH)c is deposited on a substrate, where a+b=4 or a+b+c=4, respectively, a, b and c are integers, R is a carbon-containing group and a silicon to carbon bond is indicated by Fourier Transfer Infrared analysis. The short-chain polymer is then subjected to further polymerization to form an amorphous structure of the general formula (RxSiOy)n, where x and y are integers, x+y=4, x≠0, n equals 1 to ∞, R is a carbon-containing group and a silicon to carbon bond is indicated by Fourier Transfer Infrared analysis.

Abstract: A method for etching a metal film containing aluminum, using a hard mask, and a method for forming a line of a semiconductor device using the same, are provided. A metal film containing Al is formed on a semiconductor substrate. A hard mask pattern is formed on the metal film containing Al. Next, the metal film containing Al is etched using an etching gas, including a gas containing carbon, and using the hard mask pattern as the etching mask. Preferably, the hard mask pattern is formed of an oxide film or a nitride film in which case a capping layer for the etched metal layer is not needed.

Abstract: A method for integrated management of semiconductor process data. The method is capable of easily accessing data generated in one semiconductor fabrication line, and commonly sharing and easily accessing data generated in a plurality of semiconductor fabrication lines. An integrated management system (IMS) is installed in every semiconductor fabrication lines and allows integrated management of the semiconductor process data. Each IMS is in communication with every other IMS and includes a plurality of data sets and corresponding data set modules. Then a user interface computer logs into a contacted IMS. A work environment, including a contacted data set module, is updated at the user interface computer using information from the contacted IMS. A task is then carried out at the user interface computer according to the updated work environment.

Abstract: Plasma processing apparatus frequently incorporates an antenna fed from a power supply and in this invention a power supply feeds a conventional matching circuit (10), which in turn is connected to the primary (11) of a transformer (12). The antenna (15) is coupled across the secondary winding (13) of the transformer (12) and that winding is tapped to ground at (16). This creates a virtual earth (17) near the mid point of the antenna (15) significantly reducing the variation, along the length of the antenna, in the power supplied to the plasma.

Abstract: The present invention comprises first unit cells each including PMOS transistors and NMOS transistors, each transistor having a first threshold voltage, second unit cells each including PMOS transistors and NMOS transistors, each transistor having a second threshold voltage, a unit cell array comprised of the first and second unit cells laid in array form, a power switch disposed around the unit cell array and comprised of the PMOS transistors and NMOS transistors each having the second threshold voltage, and input/output circuits disposed around the unit cell array.

Abstract: A voltage supply circuit supplies an operational voltage to plural sense amplifier arrays and includes a plurality of MOS transistors. Each transistor is located between a power supply and one sense amplifier array. A stable operational voltage is supplied to the sense amplifier circuits in each sense amplifier array, whereby a high speed operation is realized.

Abstract: An apparatus for fabricating semiconductor devices includes a spin chuck configured for mounting a wafer thereon and operative to rotate the wafer. A nozzle is arranged above the spin chuck, through which a solution is supplied to a surface of the wafer mounted on the spin chuck. A bowl surrounds the spin chuck to prevent the solution from reaching an inner wall of a process chamber. A cover is spaced apart from and confronts the spin chuck having the wafer mounted thereon. The cover has an opening through which a distal end of the nozzle passes so as to spray the solution onto the wafer surface while the cover is disposed over the wafer surface. The cover prevents any solution reflected back from the bowl from reaching the wafer surface.

Abstract: Production information for ASIC (Application Specific Integrated Circuit) devices is stored in a database of a remote host system, and data necessary for a test program which controls testers for testing the IC devices are automatically created and transmitted to a tester host. This automatic system collects the data necessary for the test condition from the remote host database; creates the test condition by comparing the collected data with a predetermined handling condition; transmits the test condition to a tester host which controls a plurality of testers using corresponding test programs; and loads the test condition into the corresponding test program. This system avoids human errors which often result when test engineers write test conditions manually, and also allows quick response to a situation when new specific IC devices are required by a customer.

Abstract: Dust proof clothing is made of a given fabric structure defined by multiple first fiber groups which are each composed of linear fibers and extend in a first direction, and multiple second fiber groups which are each composed of curved fibers and extend in a second direction intersecting the first direction. The first and second fiber groups are mutually interwoven such that an inside surface has more of the second fiber groups exposed than the first fiber groups, and such that an outside surface which is opposite said inside surface has more of the first fiber groups exposed than said second fiber groups. The dust proof clothing is worn such that the inside surface is in contact with a wearer of the dust proof clothing.

Abstract: A multiple reaction chamber system includes a transfer chamber, a load lock chamber connected to the transfer chamber, and a plurality of reaction chambers connected to the transfer chamber. An alignment chamber is connected to the transfer chamber, disposed along a path of wafer transfer from the load lock chamber to the plurality of reaction chambers, and includes a wafer aligner. A wafer recognition, disposed along a post-aligner portion of the path of wafer transfer system, recognizes an identification code of an individual wafer. A controlling system is in data communication with the wafer recognition system for selecting a selected chamber of the plurality of reaction chambers into which the individual wafer is to be transferred. Because individual wafers can be associated with each reaction chamber, a defective reaction chamber can be identified immediately and its use discontinued so that unproductive operations can be eliminated.

Abstract: A semiconductor device manufacturing method capable of coping with scale reduction of the semiconductor device and forming contact holes without deteriorating the device separation characteristics is provided. This method has the following steps. First, in the laminating process, at least a first layer, a second layer, and a third layer are formed in sequence. The second layer and the third layer are laminated over the first layer in sequence so as to cover a plurality of gate electrodes formed on the first layer. Second, in the first etching process, an opening unit is formed between the gate electrodes, and the third layer is etched using the second layer as an etching stopper. Third, in the depositing process, an insulating material film is deposited on the side wall of the opening unit and the bottom portion of the opening unit to a thickness with which the insulating material film functions as a spacer for the insulation.

Abstract: A non-volatile semiconductor memory decreases a parasitic current as much as possible without using an electric separation means. This nonvolatile semiconductor storage apparatus has multiple memory cells rows having multiple memory cell transistors M1, M2 . . . whose gates are connected to word lines WL1, WL2 . . . , respectively, and whose sources and drains are serially connected. This non-volatile semiconductor storage apparatus also has multiple column lines SBL0, SVL0, SVL1, SBL1 . . . which connect the connection nodes between the sources and drains of the memory cell transistors M1, M2 . . .

Abstract: A method of manufacturing semiconductor devices is provided, including the formation of a conductive plug and the minimizing of the step-height of an interlayer dielectric layer. An etching composition is also provided for such a manufacturing method. The method of manufacturing semiconductor devices includes the steps of forming an insulating layer over a semiconductor substrate, forming contact holes in the insulating layer, forming a conductive layer over the insulating layer to burying the contact holes, rotating the semiconductor substrate, and etching the conductive layer by supplying an etching composition on the rotating semiconductor substrate, and spin-etching the tungsten layer using an etching composition such that the conductive layer remains only inside the contact holes and does not remain over the insulating layer.

Abstract: A wafer handling apparatus prevents polymers from sticking to the handler which conveys a wafer into/from a process chamber in which the wafer is treated. The wafer handler has an arm which is rotatably driven and an effector integral with the arm. The wafer is supported on the effector via a vacuum chuck formed by vacuum holes in the effector. The temperature of the handler is controlled to be identical to that inside the process chamber. The temperature controlling system has an electric heater for heating the effector and a current supplying apparatus which intermittently supplies current to the heater to maintain the temperature of the effector. Because the temperature of the handler is maintained at least as high as that inside the process chamber, polymers floating in the process chamber are prevented from sticking to the handler.