Abstract: A method of forming an isolation trench in a semiconductor substrate includes the steps of sequentially depositing first and second insulating layers over the substrate, subsequently etching the second and first insulating layers to define active and non-active regions according to a patterned masking photoresist layer, excessively etching a part of the thickness of the substrate, removing parts of the first insulating layer by undercutting the sides of the non-active region so as to expose parts of the substrate in the active region, etching the substrate by using the second insulating layer as a trench patterned masking layer to form a trench in which the edges of the exposed parts of the substrate are rounded, depositing a third insulating layer on the bottom and side walls of the trench and the rounded parts of the substrate to repair the parts of the substrate damaged when forming the trench, depositing a fourth insulating layer over the second insulating layer so as to completely fill the trench, etchin
Abstract: A semiconductor device capacitor has a storage electrode wherein the impurity concentration decreases from the bottom to the top thereof. The semiconductor device capacitor is formed on a lower structure of a semiconductor substrate burying a contact hole formed on the semiconductor substrate. The impurity concentration linearly or non-linearly decreases going upward from the bottom of the contact hole to the top of the storage electrode. A method of manufacturing the semiconductor device capacitor also provides that the storage electrode is formed such that the concentration of impurities decreases linearly or non-linearly going upward from the bottom toward the top.
October 19, 1999
Date of Patent:
November 27, 2001
Samsung Electronics Co., Ltd.
Kyung-ho Hyun, Byung-soo Koo, Wook-sung Son, Chang-jip Yang
Abstract: A method for controlling emergency states of equipment in a semiconductor fabrication system includes determining whether on-line communication has been restored between a host computer and semiconductor fabrication equipment after an interruption in communication. If on-line communication has been restored, post-restoration emergency state data are received automatically from the equipment. Then it is determined whether the post-restoration emergency state data indicate the equipment is in a warning state. If the post-restoration emergency state data indicate the warning state, it is determined whether the warning state is a critical state. If the warning state is the critical state, a key value of a variable ID corresponding to the equipment is changed to a value indicative of shutting down the equipment. Then the equipment is shut down by inserting the variable ID into an equipment control message and downloading the equipment control message to the equipment.
Abstract: The compounds are of a class of photosensitive polymers for use in chemically amplified photoresists. These photoresists produce sharp line patterns when exposed with an ArF excimer laser. The polymer composition includes a copolymer and the photoresist composition includes a terpolymer with a photo acid generator. The resulting chemically amplified photoresist compositions have strong resistance to dry etching, possess excellent adhesion to film material, and are capable of being developed using conventional developers.
December 1, 1998
Date of Patent:
October 9, 2001
Samsung Electronics Co., Ltd.
Sang-Jun Choi, Yool Kang, Dong-Won Jung, Chun-Geun Park
Abstract: A semiconductor memory device for a package-state voltage test has a plurality of bonding pads that are electrically connected to an external device in a package state, at least one internal DC voltage generator, at least one switch connected between one of the bonding pads and the internal DC voltage generator. The switch is on during a test mode and is off during a normal mode. The switch controller is connected between at least two of the plurality of bonding pads and serves to control the switch in response to an external switching signal in the test mode. Because of this design, a number of DC voltage tests can be performed without increasing chip size since a general control pad also serves as a DC voltage test pad.
Abstract: A semiconductor apparatus includes a semiconductor integrated circuit including a conductive pattern; an insulating layer which is formed on the semiconductor integrated circuit to forms a plurality of base members having uneven heights; an opening which is formed through the insulating layer to expose a part of the conductive pattern; and a conductive layer which is formed on the insulating layer and the opening, the conductive layer is extending from the exposed portion of the conductive pattern to the top surface of the highest base member. An electrode is composed of the insulating layer, the opening and the conductive layer.
Abstract: A micro-etalon having non-beveled outer edges may be mass-produced without suffering from expected breakage problems. Such a configuration allows etalons to be mass-produced, i.e., on a wafer level. The mass-production preferably includes aligning spacer block strips to be diced with two reflective surfaces to form the etalon.
August 24, 1999
Date of Patent:
August 21, 2001
Lionel John Skillicorn, Ronald Leopold John Cowell, Warren Louis Gutheil, James Martin Schwarz, Jr.
Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area of the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.
Abstract: In a plastic packaged semiconductor device, a chip support formed on the same lead frame as leads is disposed so as to extend over the surface of a semiconductor element, the chip support is bonded and fixed to the surface of a polyimide wafer coat on the semiconductor element by means of an insulating tape, the leads are brought into contact with the polyimide wafer coat on the semiconductor element without being fixed, the leads and the electrodes of the semiconductor element are connected by means of gold wires, and these are packaged by a packaging material. Generation of crack in the sealing material thereby prevented, and the thickness of the plastic packaged semiconductor device is reduced.
Abstract: A method of forming a contact for a dynamic random access memory device is disclosed. In this method, a first insulating layer is formed on a semiconductor substrate. First and second contact pads are formed in the first insulating layer and on a semiconductor substrate in such a manner that a top surface of the first insulating layer is higher than top surfaces of the contact pads. Then a second insulating layer is formed over the substrate, which layer shows a bad step coverage. The second insulating layer is etched until the surfaces of the first and second contact pads are exposed. Then a first conductive layer is formed over the entire surface of the semiconductor substrate, and the first conductive layer is flattened, leaving some thickness of the second insulating layer. Then a second conductive layer is formed over the first conductive layer, and the second and first conductive layers are sequentially etched using a bit line forming mask, to form a bit line.
Abstract: A layout structure of a semiconductor memory device having a memory cell array region, a word line drive region proximate the memory cell array, a bit line equalization region spaced apart from the memory cell array region, an impurity region formed between the memory cell array region and the bit line equalization region electrically coupled to the bit line equalization region, and a metal line extending over the impurity region supplying a bit line equalization voltage to the impurity region, wherein a contact connecting the metal line and the impurity region is formed lateral to the word line drive region rather than between the memory cell array region and the bit line equalization region.
Abstract: An active surface of a semiconductor chip is attached to the bottom surface of a flexible circuit board having a central opening. Input/output pads on the active surface of the chip are electrically connected to a circuit layer on the top surface of the flexible circuit board through the opening. The semiconductor chip package can thus be of a size on the order of that of the chip. The circuit layer on the circuit board includes bonding pads for receipt of metal wires, land pads for receipt of terminals, and circuit traces connecting the pairs of the bonding and land pads, respectively. The input/output pads, the bonding pads, and the wires are encapsulated in an encapsulant formed by dispensing a liquid resin having a certain viscosity into the opening in the flexible circuit board. A dam around the opening prevents the liquid resin from overflowing. The flexible circuit board may further include a protective layer for protecting the circuit traces, a stiffener, or an adhesive layer thereunder.
Abstract: A semiconductor memory device is disclosed that programmably varies an output pin transmitting output data from a comparator during a test mode. Also disclosed is a read method for the test mode. The semiconductor memory device includes a comparator that compares a plurality of output data read from the memory cell array and an output pin determining unit that programmably varies a pin transmitting an output of the comparator during the test mode. Thus, when multiple semiconductor memory devices are installed in a single memory module, the output pins of the semiconductor memory devices are variously determined using the output pin determining unit so that data can be simultaneously read from more than one semiconductor memory device at a time during a test of a memory module, to thereby reduce the module test time.
Abstract: A synchronous data sampling circuit and method are provided by which it is possible to sample four data items during one cycle of a clock signal. In the synchronous data sampling circuit a first pulse signal generator receives the clock signal and generates a first pulse signal during a logic “low” interval of the clock signal. A second pulse signal generator receives the clock signal and generates a second pulse signal during a logic “high” interval of the clock signal. A first sampling unit samples first data input through the input port and outputs the sampled first data to the output port in response to the falling edge of the clock signal. A second sampling unit samples second data input through the input port and outputs the sampled second data to the output port in response to a rising or falling edge of the first pulse signal.