Abstract: A look-up-table-based programmable logic device is provided with memory circuitry which can be operated either as random access memory (“RAM”) or to perform product term (“p-term”) logic. Each individual row of the memory is separately addressable for writing data to the memory or, in RAM mode, for reading data from the memory. Alternatively, multiple rows of the memory are addressable in parallel to read p-terms from the memory. The memory circuitry of the invention is particularly useful as an addition to look-up-table-type programmable logic devices because the p-term capability of the memory circuitry provides an efficient way to perform wide fan-in logic functions which would otherwise require trees of multiple look-up tables.

Abstract: A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.

Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

Abstract: A technique is provided for improving the output drive capacity of output drivers on an integrated circuit that is configured to support I/O standards having operating voltages greater than the intrinsic core supply voltage. When MOS field-effect transistors are used in the I/O circuitry of such integrated circuits, the gate oxide layers of the transistors in the interface circuitry may need to be thicker than those comprising the core circuitry in order to tolerate I/O voltages that exceed the core supply voltage. In counteracting the degradation in output drive that may result from thickening the gate oxide layer, the pull-down signal applied to the gate of the pull-down transistor is preferably level-shifted from the core supply voltage to the higher external operating voltage associated with the I/O standard being supported. This external voltage is made available to the level-shifting circuit preferably through a spare pin or a gated I/O pin.

Abstract: A logic array block (LAB) that is programmably selectively configurable for use as a multifunction memory array is provided. The LAB is configurable for operation in at least two modes: in a first mode, each logic element within the LAB is individually configurable to perform logic functions; in a second mode, the logic elements are collectively usable as a multifunction memory array. The multifunction memory array may be addressed on a LAB-wide basis with separate read and write addresses, such that it may be configured to implement a variety of memory schemes, including first-in-first-out (FIFO) memory and random access memory (RAM).

Abstract: A static random access memory (“SRAM”) that is especially suitable for such uses as inclusion on a programmable logic device to provide programmable control of the configuration of that device. The SRAM includes a plurality of SRAM cells, all of which are simultaneously cleared to a first of two logic states by application of a second of the two logic states to clear terminals of the cells. Any cell that needs to be programmed to the second of the two logic states is thereafter specifically addressed and a data signal thereby applied which programs the cell to the second logic state. The cells are preferably constructed so that they are programmed to the second logic state by application of a data signal having the first logic state. Even a very small unipolar MOS pass gate transistor can therefore be used as the addressable path through which the data signal is applied. The memory may also include circuitry for verifying the contents of each cell via the data input terminal of the cell.

Abstract: A look-up-table-based programmable logic device is provided with memory circuitry which can be operated either as random access memory (“RAM”) or to perform product term (“p-term”) logic. Each individual row of the memory is separately addressable for writing data to the memory or, in RAM mode, for reading data from the memory. Alternatively, multiple rows of the memory are addressable in parallel to read p-terms from the memory. The memory circuitry of the invention is particularly useful as an addition to look-up-table-type programmable logic devices because the p-term capability of the memory circuitry provides an efficient way to perform wide fan-in logic functions which would otherwise require trees of multiple look-up tables.

Abstract: A programmable logic array integrated circuit device includes regions of programmable logic, regions of memory, and a programmable network of interconnection conductors for selectively conveying signals to, from, and between the regions of logic and memory. The memory regions are usable as content addressable memory. Circuitry is provided for facilitating programming of the memory in content addressable mode.

Abstract: In order to facilitate the performance of multiplications in programmable logic devices, individual logic modules of such devices are constructed so that one logic module can perform (at least) both one place of binary multiplication and one place of full binary addition. This makes it possible to reduce the number of logic modules that are required to perform a multiplication. It also reduces the number of inter-module connections employed in a multiplication, thereby tending to decrease the time required to perform a multiplication.

Abstract: A programmable logic device has plural regions of programmable logic and a general-purpose interconnection network for conveying signals to, from, and between the regions. In addition to the general-purpose interconnection network, more direct interconnections are provided from outputs of each region to inputs of one or more other adjacent or nearby regions. At least some of these direct interconnections are preferably multiplexed with more conventional inputs to the other regions so that the input resources required for each region do not become excessive. The invention is particularly useful for devices which perform basic logic using sum-of-products (“Pterm”) logic. However, the invention is also useful in other types of devices such as those which perform basic logic using look-up tables.

Abstract: Methods and apparatus for recording on DVD-like recording media in which audio content is stored in a high-capacity multi-channel (e.g., six-channel) format are provided. Various channels may use various resolutions. A two-channel audio output may be derived from the multi-channel audio data stream during playback. To facilitate an accurate derivation, the mixing coefficients to be used in generating the derivation can be supplied along with the six-channel audio data.

Abstract: A programmable logic device has a plurality of conductors extending around its periphery for use in providing at least some of the signals needed for control of input/output (“I/O”) pins which are also disposed around the periphery of the device. These control signals may include clock signals, output enable signals, clock enable signals, clear signals, or the like. The conductors that thus extend around the periphery are segmented into plural segments that can either be used independently of one another or programmably stitched together and therefore used together.

Abstract: Audio signal samples taken at different sampling rates are synchronized. A plurality of channels of audio data are sampled at different rates and recognizable synchronization data are added to selected samples of at least one channel of the plurality of channels.