Abstract: To accurately detect the short bursts of distinctive ringing signals within 100 milliseconds, a magnitude comparator produces a binary signal indicative of whether the instantaneous tip-ring voltage exceeds a predetermined magnitude. The binary signal is integrated over a predetermined period of time controlled by a timer. If the time integral is below a first predetermined value, the absence of ringing is detected; if above a second predetermined value, ringing is detected; if in between, the integrating interval is extended until the integral falls outside the two values.

Abstract: A first transistor is connected in grounded-collector-emitter-follower configuration to generate a high enough negative resistance to overcome the oscillating resistance of the crystal resonator connected to the base electrode. A second transistor connected in grounded-base configuration serves as a buffer and impedance transformer between the low impedance output of the first transistor and the high impedance of a load. An inductor connected between the resonator and the first transistor input and a variable capacitance approximating the shunt capacitance of the resonator connected across the first transitor input form an impedance inverter which absorbs the resonator shunt capacitance and converts the effect of the resonator to a parallel tuned circuit that can be broadly tuned.

Abstract: In an angle diversity receiving system, the primary and diversity signals are produced by a waveguide signal separator coupled to a single receiving antenna.The separator operates by converting selective higher order modes in the antenna into fundamental modes that will propagate in its two output waveguides. The result is a robust system that operates over a frequency band wide enough to cover both the 4 GHz and 6 GHz common carrier bands with both horizontally and vertically polarized signals, and that can use a wide variety of antennas.

Abstract: In a receiver for receiving and decoding a baseband multilevel signal into a digital data signal, and A/D converter produces in addition to the decoded data bits a "soft" bit, which inherently indicates the error polarity of the baseband signal. The soft bits are binary added to the most significant data bits to produce a sum bit. The sum bits are integrated, and the integral is used in a feedback loop to control the baseband signal amplitiude.

Abstract: To produce a high current carring inductor with a high inductance value in space normally too small, a transformer is chosen which meets space requirements and has a primary winding of sufficient current capacity, but too little inductance. A bidirectional current source drives the secondary winding under control of a feedback circuit in response to sensed primary winding current to effectively multiply the primary winding inductance.

Abstract: Maximum frequency range in a VLSI voltage controllable crystal oscillator is obtained with a two-stage amplifier with feedback across both stages. The first stage is implemented by an MOS transistor connected in source-follower configuration to minimize input capacitance, and the second stage is implemented by a bipolar transistor to provide the needed gain. A bidirectional voltage limiter connected to a crystal node limits the oscillations to a symmetrical waveform. The bias of an output buffer amplifier may be selectively shifted to maintain optimum duty cycle with the different triggering levels of diverse logic driven by the oscillator, and the bias may be dynamically driven by an analog signal to provide a duty cycle-modulated output.

Abstract: Maximum frequency range in a CMOS voltage-controllable crystal oscillator is obtained with a two-stage amplifier with feedback across both stages. The first stage is connected in source-follower configuration to minimize input capacitance, and the second stage provides the needed gain. To eliminate body effect, the source electrode and body of the second stage CMOS device are connected together. A bidirectional voltage limiter connected to a crystal node limits the oscillations to a symmetrical waveform. Changes in effective duty cycle caused by the different triggering levels of diverse logic connected to the oscillator output are compensated for by selectively shifting dc bias to a buffer amplifier.

Abstract: A digital synthesis technique provides pulse shaping in accordance with predetermined time domain and frequency domain constraints. In the technique, the informational content of a binary bit stream is used by an access circuit (12) to form address words for accessing a read-only-memory (13). The digital representations stored in the ROM (13) represent a superposition of temporally-displaced truncated impulse time functions, each weighted by the discrete transmission symbol levels of the analog output signal. The digital representations from two ROMs (13-1 and 13-2) are toggled by a sequencng circuit. In other embodiments of the invention, different memory arrangements ranging from a signal ROM (142) to an array of ROMS (163-1 through 163-3 and 164-1 through 164-3) are respectively used to decrease circuit complexity. In a digital radio transmission application of the technique, this arrangement is economical, readily reproducible and stable since it obviates the need for conventional complex analog filters.

Abstract: Contactless inductive power transfer from a stationary "reader" to energize the electronics on a portable data or "smart" card is made practical through a flexible inductor carried on the card. The inductor, which acts as the secondary portion of a power transformer, comprises a flat coil and a flexible magnetic but nonmagnetostrictive core piece. The core piece may be a thin wafer of amorphous magnetic alloy. Clock pulses to synchronize data transfer on the card with the reader can also be generated from the signal picked up by the inductor.

Abstract: To provide accurate insertion of a circuit board into a high density socket in an equipment frame, a lever arrangement is mounted to the circuit board near its upper front edge on a pivot. Rotational force applied to a first lever arm causes a second arm to engage the frame, translating the rotational force to insertion force acting at the pivot. The combination of the acting insertion force and the insertion resisting force of the socket set up a moment couple. The moment couple tends to rotate the circuit board, forcing a reference surface on the board against a mating reference surface on the socket during insertion.The lever arrangement also provides mechanical advantage for extraction and, by using the resilience of the board, latching. The lever also doubles as a faceplate to protect and beautify the equipment.

Abstract: The most significant bits of each input word of a linear PCM signal address a read-only memory (ROM). Stored at each ROM address is a table of instruction words, one instruction word for each bit in the output word. The instruction words direct a switch to select each bit for the output word from a choice of 1, 0, or an input bit PCM compression according to a predetermined characteristic is implemented by instruction words which direct selection of the proper chord bits from 1 or 0 and the proper step bits from the input bits. A different compression characteristic may be implemented by a different set of stored instruction words. The instruction words also command selective bit inversion and selective inclusion of the bit in a parity check. Implementation of the translator with commercially available hardware is described.

Abstract: An audio program signal is converted into 12-bit PCM words and two 12-bit words are inserted into three 8-bit time slots in a T1 line. To avoid interference from a "yellow" alarm in which the second bit positions of all of the 8-bit time slots are pre-empted, the three least significant bits are placed in the second, sixth and tenth bit positions of the 12-bit words, which alone can occupy the second bit position of the 8-bit time slots.A translator for generating the 12-bit words from 14-bit linear PCM words is described. The six most significant bits of the 14-bit words address a ROM. Stored at each address in the ROM is a table of twelve instruction words. Each instruction word causes a selector switch to choose a bit of the output word from 1, 0 or an input bit. Bit order of the 12-bit words is therefore controlled by the order of instruction words in the tables of the ROM.

Abstract: To insure timing recovery, T carrier requires that the signal contain no more than fifteen consecutive zeros and a "1"s density of at least one out of eight. When a 15 kHz audio program signal is converted into 12-bit words and four words inserted into six 8-bit time slots of the T1 line, timing recovery requirements have been met by using, in addition to an even parity bit, a dedicated "1" bit.Here, instead of the usual eight chords, the compression characteristic used in generating the 12-bit words has only 7 chords, each represented by a combination of three chord bits that always includes at least one "1". This frees the dedicated "1" bit for additional coding detail. Centrally locating the chord bits within the 12-bit word further allows a mix of voice and program channels in the one channel bank.In a disclosed implementation, the analog samples are first converted to 14-bit linear PCM words, and then digitally translated into 12-bit compressed words.

Abstract: A very low power asymmetrical polarity marking signal which may be the sum of a cosine wave and its coherent second harmonic is added to a symmetrical message signal before transmission. At the receive the polarity information may be recovered from the average dc value of the positive and negative peaks of the polarity signal or from the coincidence of peaks of the fundamental and second harmonic components.

Abstract: A multiterminal socket suitable for mounting on a printed wiring board together with one or more jumper plugs is disclosed for providing various circuit options. The jumper plugs have a pair of interconnected male terminals projecting from one end and a pair of resilient extensions straddling the male terminals. When a plug is inserted in a correct socket position the plug extensions flex outwardly to pass over a pair of socket shoulders and lock the plug in place with a snap action. When an attempt is made to insert the plug in an incorrect position which would cross-connect circuits, a pair of opposing projections on the socket body interfere with the plug extensions to prevent insertion. Double throw switching functions and single throw functions with idle plug storage are described together with a visual indication of the option in effect.

Abstract: Feedback amplifiers having zero or infinite input and output impedances are used as the main amplifier and error amplifier elements of a feed-forward amplifier system. This allows the required impedance matching with simple resistive coupling networks rather than the complicated couplers heretofore required.The use of both series and shunt feedback provides convenient coupling points for the proper phase relationship between combining signals, and the unidirectional conductivity of the amplifier transistors supplies the directionality usually required of the couplers.

Abstract: A push-pull transistor amplifier wherein the transistors are biased in the Class A region but near collector saturation. An inductance is series coupled with the collector source to permit the amplifier to handle large peak-factor signals. A diode is connected in parallel with the collector-base junction of each transistor to prevent charge storage effects.

Abstract: Current and voltage feedback are used in separate frequency dependent major loops around a high gain broadband amplifier to produce frequency shaped gain and matched input and output impedances.

Abstract: The pass transistor of this series regulator supplies current at a regulated voltage only sightly below its unregulated supply voltage. The driver transistor, driven by the feedback loop, is supplied from a higher voltage source. During periods when the pass transistor cannot supply the load because its source voltage is too low, the driver transistor supplies the load through the base-emitter junction of the pass transistor without affecting the regulation.