Abstract: A packet classifier within a network adapter detects an application packet header belonging to a packet in a data stream associated with an application that uses a network protocol, such as TCP/IP, SNA or IPX. Offsets included within the application header are identified and a plurality of registers is loaded with the identified offsets. Each of a plurality direct data placement patterns are masked with contents of the loaded registers. Each direct data placement pattern is associated with an application packet header and includes a corresponding I/O context. Additionally, each direct data placement pattern includes a corresponding connection path for direct placement of a payload corresponding to the detected application header in a memory that is utilized by the application.

Abstract: A multimedia search and indexing system automatically selects scenes or events of interest from any media, i.e., video, film, sound for replay, in whole or in part, in other contexts. The entire audio track of a recorded event in video, film, sound, etc., is analyzed to determine audio levels within a set of frequency ranges of interest. Audio clip levels within the selected frequency ranges are chosen as audio cues representative of events of interest in the track. The selection criteria are applied to the audio track of the recorded event. An Edit Decision List (EDL) is generated from the analysis of the audio track. The list is representative of scenes or sounds of interest as clips for reuse. The clips are reviewed and accepted or rejected for reuse. Once selected, the clips are edited using industry standard audio and video editing techniques.

Abstract: A reactively controlled directive antenna array that has a single central monopole or dipole as a radiating element excited directly by a feed system. A plurality of parasitic elements surround the radiating element and through changing the state of the parasitic impedance causing the antenna to be in an omni directional or beam pointing mode according to whether the parasitic elements are open circuited or short circuited. A computer modem and memory including stored programs control the antenna array in an omnidirectional or directive mode to locate, identify and communicate with nodes in a wireless communication network. A stored table is created in the memory indicating the antenna direction for communicating with each node in the network. Using the stored table, the computer initiates a communication sequence with a selected node, the sequence having the advantages of improved signal sensitivity and angular discrimination for wireless communication systems.

Abstract: A communications adapter receives and transmits simultaneously packet and/or isochronous data between two interfaces; a network and a host bus system. The adapter stores the isochronous and packet data in receive and transmit queues configured in a FDDI RAM buffer. A controller manages the transfers of the data into and out of the queues. A local bus interacts with the system to provide descriptors of addresses in the system for transfers of data out of the queues to the system or the network. The controller is programmable to provide a variable threshold for the transfer of data between the queues and the system or the network. A systems interface unit handles the transfer of data to/from the system and allows data to bypass the queues and directly access the system or the network.

Abstract: A system and method for passively measuring and correcting ring latency on a token or FDDI ring includes generating bits and token frames in a defined pattern according to the token ring protocol. A passive device coupled to the token ring measures CMIN, the minimum spacing, CMAX, the maximum spacing in bits and calculates Fi the frequency of changes in Cmin and Cmax between successive tokens or a token and a frame on the ring. A latency event vector Li is generated by the passive device. A controller responsive to the latency vector Li corrects the spacing between successive tokens or a token and frame to achieve a constant ring latency regardless of electrical or operational changes on the token ring.

Abstract: A power bus digital communication system reduces power and signal cabling in a space satellite by transformer coupling digital signal sources to power bus circuits, the transformer coupling devices in all power bus circuits being in parallel relation and electrically isolated from a power supply whereby the digital communication sources may communicate among themselves at a DC power level using a square wave modulated according to a Manchester code.

Abstract: A method dynamically changes the bit rate or bandwidth of constant bit rate data structures in an Asynchronous Transfer Mode (ATM) communications environment. The method defines within a data channel a Change indicator (CI) indicative of an end user's request for a bit rate change within said data structures. The Change Indicator is continuously transmitted from a source side to a destination side in the ATM environment, along with the data structures on said data channel. Upon receipt at the destination side of a user's request of a bit rate change, the destination side modifies the value of said Change Indicator. The source side, acknowledges the modification of the value of the Change Indicator, whereby the transmission of data structures continues on the data channel with a new constant bit rate.

Abstract: A hardwired, dynamically reconfigurable counter array counts occurrences of different traffic events having different rates of occurrences monitored on a high speed data network by an Event Driven Interface (EDI). The array includes a plurality of "N" bit counters, where "N" is a binary multiple. The counters are arranged in an array of size "m,n", where "m" is the number of rows and "n" is the number of columns in the array. A signal input is provided to each counter as a first input, each signal being definitive of a specific traffic event occurring on the high speed network. Each counter is connected to the adjacent counter in the column through a multi-terminal logic element, each logic element in a column receives the output of a counter as a first input and provides an output to the succeeding counter as a second input. A counter logic switch responsive to an input signal generates a counter logic vector as an output.

Abstract: An ATM communications network includes a system processor having a device driver and a memory coupled to an adapter at an interface. Frames stored in the memory are transmitted to the network using a transmit ready queue residing in the adapter and defined by transmit control registers. The frames are linked together by descriptors and pointers to received ready lists maintained by the device driver. A transmit frame complete list is established in the system memory using the transmit control registers. An interrupt is generated by the adapter indicating when frame transmission is complete. Simultaneously, cells are received from the network and stored in system memory according to a free buffer list established by the device driver. A pointer is maintained by the device driver to the last entry of the receive free buffer list. The adapter maintains a pointer to the next buffer to be used from the receive free buffer list.

Abstract: A high speed, serial pattern detector, uses parallel finite state machines to analyze sequential bits in a serial bit stream. Single bit random access memories store the single bit of the next address to be used in detecting the sequence.

Abstract: A method of switching multimedia data streams in response to requests to allocate or deallocate a user on a network receiving those data streams is herein described. The data streams are transmitted in master cycles, portions of each master cycle being allocated to each user. The relationship between the user and the portion of the master cycle is kept track of by means of a matrix method.

Abstract: The realtime event classification technique is described for a data communications network, which enables the categorization of data frames based upon selection significant bit segments in the serial bit stream. A base Event Driven Interface and an extension Event Driven Interface are both coupled to the data communications network, to identify patterns in the serial bit stream. The base Event Driven Interface identifies patterns which correspond to events which are to be counted. The extension Event Driven Interface identifies patterns of bits which are selection significant for the types of categories which are desired to be monitored. A plurality of event vector counters have event inputs coupled to the base Event Driven Interface and have a selection input coupled to the extension Event Driven Interface. A selection signal output from the extension Event Driven Interface enables one of the plurality of the event vector counters to receive the event signals from the base Event Driven Interface.

Abstract: A data processing system includes branch prediction apparatus for storing branch data in a branch prediction RAM after each branch has occurred. The RAM interfaces with branch logic means which tracks whether a branch is in progress and if a branch was guessed. An operational code compression means forms each instruction into a new operation code of lesser bits and embeds a guess bit into the new operational code. Control means decode the compressed operational code as an input to an instruction execution unit whereby conditional branch occurs based on the guess bit provided a branch instruction is not in progress in the system.

Abstract: An apparatus and method for increasing the mean time between failure for computer systems is disclosed. A single spare line can be used to replace any of several signal lines. Using 2:1 multiplexers, defective signal lines can easily be switched to a nonoperative state and the remaining signal lines shifted to provide for replacement of the defective line without significant path length increase or signal time delay. The invention is applicable to signal paths of different varieties, including electrical, electro-optical and fluidic.

Abstract: The method enables realtime establishment and maintenance of a standard of operation for a data communications network. The process begins by monitoring the network over some period of time to build benchmark data sets. The benchmark data sets contain a standard of operation for the network, which is historically categorized by either traffic type or activity. This standard of operation is accumulated by the intelligent monitoring facilities. After a period of accumulation, the benchmark is used to determine whether data taken from current monitoring activity indicates normal network behavior. Network monitoring information is analyzed using criteria in modules that have an interface to an expert system. The criteria modules evaluate the current monitored data against the prior benchmark collected data. The criteria module determines if the current network operating characteristics are outside the bounds of normal behavior. If they are, then alerts and logs of information can be sent to the expert system.

Abstract: A coordinate processor for a computer system having an absolute position pointing device (10) such as a touch sensitive display screen comprises stimulus detection means (200) for detecting a tactile stimulus of an absolute position pointing device (10) and directed to a point within a data display area (610) of a computer system. The processor further comprises coordinate locking means (210-320) for locking a current cursor position to the point within the display area corresponding to the tactile stimulus in response to said stimulus exceeding a predetermined threshold value. The processor permits the computer system to distinguish a stimulus of the pointing device (10) for repositioning the cursor within the data display area (610) from a stimulus of the pointing device (10) for issuing a button click command to the computer system. The processor may be embodied in an electronic logic circuit within a pointing device adapter portion of the computer system.

Abstract: A method and system for call set-up and channel resource allocation between a plurality of parties in a multi-media conference call that consists of receiving notice that a Sender (the initiator of the conference) wants to commence a video conference. At that point, the number of channels required by the proposed call is determined. Subsequently, each requested participant is identified as available, busy, or no answer. If the receiver is available and sufficient channels are available, the call is set-up and the present members of the conference are notified of what channel each should transmit on and what channel(s) to listen to for the other participants. As each receiver is added, the Sender may conference with the present Receiver. If it is decided at this point, that the receiver will not participate in the conference, the call to that receiver may be terminated, and the procedure continues for other receivers until the full conference is set up. Individuals may leave the conference at any time.

Abstract: A programmable hardware adapter for switching between two or more levels of arbitration priority for devices connected to a communications bus without host processor intervention. The adapter is programmed with an external arbitration value at initial program load. A control bit selects whether the arbitration level within the adapter is used for arbitration or if the device's internal arbitration level is used. When the external arbitration level is used to vie for the bus, the adapter's state machine sends a signal to the device to tell it it won or lost, depending on the outcome of the arbitration.

Abstract: A Micro Channel integrated circuit design capable of controlling high speed data and control transfers between a Micro Channel bus, a local processor, and a dedicated local data bus. The interface controller utilizes enhanced features of the Micro Channel and data buffering to achieve high speed data communications with various bit size Micro Channel devices. Queued commands are handled by flexibly programming the interface control operations. Interface control hardware increases the processing speed of data transfers by implementing performance critical functions of queuing in hardware. Extensive error checking and reporting and self-test give the interface controller advance functions as an input/output processor.

Abstract: A system and process are disclosed that allows the collection of events to be organized and ordered so that relationship between events and the events themselves can be identified as a state or series of states which describe and allow control of performance aspects of protocol activity. The architecture allows dynamic programming of multiple of devices for the purposes of coordination and correlation of events such that monitoring, performance analysis and control can be accomplished on a real-time basis for any speed network. The architecture facilitates feedback of the correlated events for the purposes of monitoring and controlling network activity.