Abstract: Disclosed is a simplified method of producing semiconductor device structures in an integrated technology using at least one ion implantation step. Implantation of the doping ions into a silicon wafer, for example, for producing a subcollector or an emitter, is not effected, as previously, in an ultra-high vacuum atmosphere through a thin protective layer of silicon dioxide which is applied by a separate thermal oxidation step prior to implantation, but the doping ions are directly implanted into the bare silicon wafer. The latter implantation is effected in an atmosphere of increased partial pressure of oxygen. Enhanced diffusion of the oxygen adsorbed at the surface occurs into the vacancies which are generated by the implanted doping ions close the surface of the silicon wafer. In this manner a silicon dioxide protective layer is formed already in the initial stage of ion implantation.

Abstract: The mutual alignment of mask and substrate patterns of a specific semiconductor structure are attained by use of a plurality of individual marks in a specific geometric position with respect to each other. By the arrangement of openings in the alignment pattern of the mask, the broad electron beam is split into a multitude of individual beams which interact with alignment marks on the substrate. The interaction is used to generate a coincidence signal. The signal to noise ratio of this arrangement is determined by the overall current and is comparable to that of a thin concentrated electron beam. Registration is effected in a small amount of time and the disadvantageous effects of the high current density used in the raster process are not a factor. In a preferred embodiment, the alignment pattern of the mask is a matrix with center spacings of openings increasing upon advance in two directions perpendicular to each other such that no distance can be represented by the sum of smaller distances.

Abstract: Complementary, vertical bipolar NPN and PNP transistors are fabricated on the same monolithic semiconductor substrate which have matched high performance characteristics. A method for fabricating such complementary devices is also provided. In the method, a barrier region of a first conductivity type is formed on the surface of the monocrystalline semiconductor substrate doped with a second conductivity type. After an annealing heat treatment to drive in the doping ions of the barrier region, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. The collector region for the other complementary transistor is formed within at least one other isolation region.

Abstract: A mask for structuring surface areas and a method for manufacture thereof. The mask includes at least one metal layer with throughgoing apertures which define the mask pattern and a semiconductor substrate for carrying the metal layer. The semiconductor substrate has throughholes that correspond to the mask pattern. The throughholes in the semiconductor substrate extend from the metal layer-covered surface on the front to at least one tub-shaped recess which extends from the other back surface into the semiconductor substrate. Holes are provided in a surface layer in the semiconductor substrate. The surface layer differs in its doping from the rest of the substrate and the holes which are provided in the surface layer have lateral dimensions larger than the apertures in the metal layer so that the metal layer protrudes over the surface layer.

Abstract: The invention relates to a semiconductor device and to a method of fully eliminating lattice defects in N-conductive zones of a semiconductor device which are generated by ion implantation of phosphorus. According to the invention, conductivity-determining ions like antimony or arsenic are implanted into phosphorus-doped zones of a semi-conductor device. A dosage of 1 to 10% of the phosphorus dose is used. The implantation of the antimony or arsenic takes place with the same, or with a greater implantation depth than the phosphorus depth. Subsequent to the antimony/arsenic implantation the device is annealed in an inert gas atmosphere at approximately 1000.degree. C.

Abstract: A method for doping silicon bodies by the diffusion of boron into the bodies is described. The method is an improvement of processes where the silicon bodies are exposed in a first heating process to a gas mixture containing a predetermined boron quantity and boron and oxygen in a predetermined quantitative ratio and a second heating process is used to drive the boron into the silicon. In the method, a borosilicate glass layer and a boron-rich silicon dioxide layer are removed by first immersing the silicon body in hydrofluoric acid diluted with water and subsequently in an aqueous sulfuric acid/potassium permanganate solution.

Abstract: A process for forming a layer of a metallurgy interconnection system on a substrate. The process involves forming a first electrically insulative layer of an organic polymerized resin material on the substrate, forming a second thin layer on the first layer which is resistant to dry etching conditions which are effective to etch the first layer, depositing a photoresist layer on the second layer, exposing the photoresist to form an inverse pattern of a desired metallurgy pattern and developing the photoresist, reactive ion etching the resultant exposed areas of the first and second layers, depositing a blanket continuous conductive metal layer over the hills and valleys of the pattern resulting from reactive ion etching, applying a planarizing photoresist layer, etching the photoresist to expose high spots of the metal layer, and etching the metal high spots to a depth sufficient to expose the surface of the second layer.

Abstract: An implanted resistor structure for semiconductor integrated circuit devices is formed by a double ion-implantation providing a high breakdown voltage resistor.

Abstract: An optical system and technique for monitoring a monotonic change in the thickness of a transparent film by means of optical interference, and for eliminating ambiguity in the identification of absolute film thickness. The system is particularly adapted for monitoring the etching of a dielectric film of uncertain initial thickness in microelectronic fabrication. The technique utilizes a white light source directed upon the film. Reflected light, modified by optical interference in the dielectric film, is monitored by photodetectors at two distinct wavelengths. The cyclic patterns of intensity change at the two wavelengths are compared to identify unambiguously the absolute thickness of the film, although the initial uncertainty in film thickness may have corresponded to several cycles of either wavelength pattern alone.

Abstract: In an ion implantation apparatus, a beam defining member such as the acceleration plate is constructed such that the member is maintained at a temperature above the condensation point of the vapor emanating from the source of charged particles, thereby preventing the vapor from condensing on the member and providing a self-cleaning effect.

Abstract: An electrical package for Large Scale Integrated (LSI) devices includes a carrier having (a) thermal expansion similar to a semiconductor, (b) a standard array of terminal pins (100 or more) and (c) a circuit transposer that is (i) a semiconductor material, typically silicon and (ii) readily personalized to connect any combination of attached LSI devices to the input-output terminal pins. The package utilizes solder technology to interconnect the carrier, circuit transposer and LSI devices. The carrier and semiconductor transposer eliminate mechanical stress on the solder joints that would otherwise occur from thermal coefficient expansion (TCE) mismatch between dissimilar package materials. The circuit transposer increases the wirability of electrical packages utilizing solder technology. Reliability problems presented by thick film paste or metallized conductors on carriers are also overcome by the semiconductor circuit transposer.

Abstract: Apparatus for determining the AC or switching delay behavior of an LSI circuit. The apparatus measures the signal propagation along different circuit paths to determine the AC characteristic. Each LSI circuit line under test is connected to a display through a line counter logic block. Each line counter logic block responds to a begin count pulse, counter pulses and stop or reset pulses. The logic block provides numerical count to the display until the line under test switches. The numerical counts on the display for the various lines indicates the AC performance of each circuit as they respond to input data over a selected timing interval.

Abstract: A metal gate transistor is fabricated to have reduced gate overlap of source/drain regions and increased oxide thickness over the diffused regions whereby parasitic capacitance is reduced and switching speed is increased.

Abstract: A semiconductor memory or storage circuit includes cross coupled transistors and isolating transistors operating at a first threshold voltage and load transistors for the cross coupled transistors operating at a second threshold voltage. The storage cell is disposed in a matrix of word and bit lines. The load devices are connected between a supply voltage and the cross coupled transistors which are returned to a reference potential. The isolating transistors are connected between the cross coupled transistors and adjacent bit lines. The word line is connected to the gates of both the isolating transistors and the load devices. When the word line is down, the isolating transistors are turned off and the load devices supply sufficient current to retain the stored information in the cross coupled transistors. When the word line is raised, the gate voltage of the load transistors is raised to supply additional current to the circuit.

Abstract: Noise from track retarders is significantly reduced by a brake shoe which dampens vibrations as continuous braking action of a wheel occurs. The brake shoe is adapted to have selectively variable brake surface configurations which contribute to reduced vibration. A special metal alloy, typically a flake-graphite bearing iron with vibration suppression characteristics lubricates the braking surface and lessens wheel oscillations during braking. The lubrication also contributes to uniform surface temperatures along the braking surface which lessens the tendency for the braking to fade. The brake shoe is basically a self-lubricated surface of variable contact area configuration.

Abstract: A standard logic array can be electrically altered at different time intervals to execute complex logic functions. Input variables to the array are processed in a network to generate sets of implicants of a complex function in one or more time periods. The implicants constituting the function are processed through a logic network or matrix as the logic personality of the matrix is altered. The implicant and logic networks may be personalized by (a) structure, (b) time signals, (c) personality signals, and (d) any combination of (a), (b) and (c). The standard array executes complex functions in a single time period or by processing one or more implicants in groups at different time periods. The testability of the array may be improved by appropriate interconnections of the array elements. The invention reduces the number of logic elements or part numbers a system designer must assemble to achieve desired objectives for a data processing machine.

Abstract: The package comprises a plurality of metal/polymer laminates whereby electronic components or functional units may be directly attached or plugged into laminated elements to form a unitary package. An element or thermal transposer is included in the package to minimize thermal expansion mismatch between the components and the laminates and conduct thermal energy away from the attached electronic components. The polymer laminates are selected to have a configuration and thermal coefficient of expansion (TCE) that will permit the insertion and locking of materials within the laminates to form the unitary package. A wide variety of components and functional units having different electrical, thermal characteristics may be included in the package. The package is amenable to mass production processes that may be controlled by a designer to obtain packages at a low cost, more flexibility and suitable for complex electronics system.