Abstract: A device for removing a heatspreader from an integrated circuit package (ICP) according to the present invention. The device includes a base piece that is preferably made of a suitably rigid and thermally conductive base material such as tool steel. The base piece defines a base cavity that is adapted to receive and engage the heatspreader. The depth of the base cavity is approximately equal to a thickness of the heatspreader. The device further includes a top piece comprised of a suitable top material such as tool steel. The top piece includes a body portion from which an elongated member or handle extends. The body portion of the top piece defines a top cavity adapted to receive and engage the integrated circuit package. The elongated member is suitable for manipulating the body portion of the top piece to apply a torquing force to the ICP package when it is engaged in the top cavity.

Abstract: A toothbrush including an elongated handle, a bristle head, a plurality of bristles, and an electronic device. The elongated handle includes a recess suitable for housing an electronic device. The bristle head is connected to the elongated handle. The plurality of bristles are embedded in the bristle head. The electronic device is configured to produce a detectable output sequence after a condition has been satisfied. In one embodiment, the detectable output comprises an audio signal while in an alternative embodiment, the detectable output comprises a visual signal such as light. In one embodiment, the electronic device includes a sequence initiator, a timer, and an output device all coupled to a control unit. The control unit is preferably adapted to initiate the timer upon receiving an initiation signal from the sequence initiator. The control unit is further configured to receive a signal from the timer after a minimum specified duration has expired.

Abstract: A process for fabricating a gate dielectric stack of a MOS transistor. A native oxide film is formed on an upper surface of a semiconductor substrate. A silicon nitride layer is then deposited on the native oxide film. A final dielectric film is then formed on the silicon nitride film. A dielectric constant of the final dielectric film is in the range of approximately 20-200. The substrate is then annealed in an inert ambient to produce the gate dielectric stack. An equivalent silicon dioxide thickness of the dielectric stack is typically in the range of approximately 5-20 angstroms whereby a gate dielectric stack suitable for use in deep sub-micron transistor is fabricated with a film thickness substantially in excess of an electrically equivalent silicon dioxide film. A suitable material for the final dielectric film includes oxides comprising oxygen and an element such as beryllium, magnesium, calcium, zirconium, titanium, or tantalum.

Abstract: A semiconductor process for forming a gate electrode of an MOS transistor. A gate dielectric is deposited on an upper surface of a semiconductor substrate. A dielectric constant of the gate dielectric layer is in the range of approximately 25 to 300. A thickness of the gate dielectric is in the range of approximately 50 to 1,000 angstroms. A conductive gate layer is then formed on the gate dielectric layer. A first nitrogen distribution is then introduced into the gate dielectric layer. The introduction of the first nitrogen distribution is typically accomplished by implanting a first nitrogen bearing species into the gate dielectric layer. Ideally, a peak impurity concentration of the first nitrogen distribution is located at an interface between the semiconductor substrate and the gate dielectric layer. Thereafter, a second nitrogen distribution is introduced into the gate dielectric layer.

Abstract: A semiconductor wafer comprising a single crystalline lattice suitable for use in the manufacture of integrated circuits, namely computer chips and dies, wherein a diameter of the wafer is greater than approximately 150 millimeters and wherein the wafer includes a first hole extending through the wafer. The hole is adapted to facilitate handling of the wafer without directly contacting a surface of the wafer. The wafer preferably includes a primary flat and the first hole includes a flat side having a predetermined and known orientation with respect to the primary flat of the wafer. In one embodiment, the wafer further includes a guide hole formed near the first hole such that the center-points of the first hole and the guide hole are oriented with a predetermined and known orientation with respect to the primary flat of the wafer.