Abstract: A phase-lock loop (PLL) circuit provides fast locking and low spurious modulation jitter through “gearshifting” control. The gearshifting PLL combines the advantages of low jitter from integer-N PLL and fast locking from fractional-N PLL. The PLL circuit includes a phase/frequency detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO). Control of the PLL circuit includes configuring the PLL circuit in two configurations, one for each phase of operation. The bandwidth of the loop filter is increased during the first phase of operation and the circuit is locked to a frequency that is close to the desired output frequency. During the second phase, the bandwidth of the loop filter is decreased and the circuit is locked to the desired frequency. The first configuration provides a relatively fast lock time compared to the lock time provided by the second configuration. The second configuration provides more stability than the first configuration.

Abstract: A semiconductor device such as a photodetector has a substrate having an active region layer containing an active region of the device. A dielectric layer is disposed on the active region layer, and a metal active region contact is disposed in the dielectric layer above the active region and electrically contacting the active region. A metal electrostatic discharge (ESD) protection structure is disposed in the dielectric layer around the active region contact, wherein the ESD protection structure electrically contacts the active region layer of the substrate to provide an ESD discharge path for charge on the surface of the dielectric layer.

Abstract: An electronic package is adapted to be coupled in a single-ended configuration and in a differential configuration. The package provides a characteristic impedance of approximately 50 ohms when configured in a single-ended mode and also when configured in the differential mode. The package includes multiple terminals, which are coupled to ground, S, and {overscore (S)}. The package may be configured externally by the user for either mode. The package may also be fabricated to be coupled in either the differential mode or single-ended mode for user specific applications.

Abstract: A low noise band-gap voltage reference utilizes pairs of NPN and PNP transistors operable with supply voltages of less than 3 volts. This voltage reference utilizes pairs of bipolar transistors. Each pair has a NPN and a PNP transistor configured such that the base of the NPN transistor is coupled to the emitter of the PNP transistor. The base of the PNP transistor of each pair is coupled to the emitter of the NPN transistor of another pair. Collectors and emitters of the transistors are coupled to current sources providing current proportional to absolute temperature. The transistors are configured such that the largest voltage developed across the core of transistor pair is approximately equal to the band-gap voltage.