Abstract: A system is provided for synchronization between a host processor and a video interface having display terminal(s) and/or digital printer(s). The video interface is made self-adjusting with the reference synchronization signal of the video terminal which are provided by the host processor. A pixel clock in the video interface is recalibrated to a higher clocking rate and used for sampling the incoming data signals to identify the precise center of the data signals. The timing relationship betweeen the video interface clock signals and the host sync signals is then determined and stored, the resulting synchronization permitting the video data signals to be sampled in their precise center and thereby enhance the operation of the digital printer without manual intervention of service personnel.

Abstract: Cathode ray tube apparatus including compensation (14) for the vertical component of terrestrial and of other ambient magnetic fields (15). The compensation is achieved by the generation of an opposing vertical magnetic field by energization of the degauss coil (11, 12) in the apparatus. Two embodiments are described: one applies a continuous direct current (21) after the degaussing operation and the other applies a direct current component coincident with the degaussing signal to permanently magnetize components of the apparatus. The magnitude and polarity of the compensation provided may be variable.

Abstract: A system for interconnecting an intelligent controller to a plurality of terminal devices includes a software module, a microprocessor and a device adapter having a plurality of output ports. The system operates under the control of said software module. When the system is powered up, a status for the output ports is assumed and tested under control of a configuration register. If the test is successful, the terminal port remains in that state; if unsuccessful, the state of the terminal port is reversed. The system permits an exchange of operating modes in the terminal devices associated with one port without adversely affecting operation of the remaining ports in the system.

Abstract: A raster-scanned interlaced cathode ray tube display is refreshed from a bit buffer (1). Cursor control logic (17) compares the refresh address (3, 4) with a desired cursor address and generates cursor defining bit patterns in synchronism with the bit pattern derived from the bit buffer (1). The cursor control logic (17) also generates overlay information (25) to control the mixing of the bit streams in mixers (11, 12, 13) to produce a 2 or 3-pel wide cross-hair cursor on the CRT screen. The cursor lines can be black, white or transparent. The overlay signal may also be used to control a further optional mixer combining the composite cursor bit-buffer bit patterns with bit patterns derived from a coded character buffer containing coded alphanumeric characters to be displayed.

Abstract: A display processor in a raster graphics display system includes a transformation, clipping and mapping feature which controls the transformation, clipping and mapping of graphics data. A control byte contains 5 bits identified as: M--Window to viewport mapping; P--perspective projection; D--2D/3D mode; T--transformation; and C--clipping. Each bit in the control byte is tested to determine what operations are to be performed on the figure to be drawn.

Abstract: Assuming that a given equation representing a quadratic curve is:F(x, y)=ax.sup.2 +bxy+cy.sup.2 +dx+ey+f=0,the method for generating quadratic curve signals repeatedly selects a point close to F (x, y)=0 in only one of either the region of F (x,y).gtoreq.0 or the region of F (x,y)<0. This method allows to generate quadratic curve signals by using only a few parameters and without using complicated calculations. A hardware implementation is also disclosed.

Abstract: A CPU initializes pluggable adapters with built-in identity and conditional ROS and complies a Hardware First Level Interrupt Handler (HFLIH) table of identity against status register address and a Software First Level Interrupt Handler (HFLIH) table of identity against on-board system function. It stores the tables with a control module in enabled memory on the keyboard adapter. Conditional ROS is enabled on a given adapter receiving a broadcast of its own identity. Adapter interrupts are ORed. HFLIH is stepped through by the control module to access adapter status sequentially, servicing each adapter in turn from its ROS, using its broadcast identity. The enabled adapter appears as a single entity to the central processor and occupies a single window in the address space which is common to all of the adapters but used by only one at a time. System functions are accessed via HFLIH.

Abstract: A drive device of the type utilizing the property of shape memory alloys comprising a first wheel (12) and a second wheel (16) drivingly coupled together by means of a wire loop (20) of a shape memory alloy and a generator and/or a fan (7) coupled as an integral part of the drive device in such a way that a forced cooling of the wire loop (20) is obtained.

Abstract: A d.c. power supply system comprises a plurality of voltage regulating power supplies connected in a master slave configuration, the number of regulators being one greater than required to provide load current requirements. The master regulator generates a control signal to control the output of the individual slave regulators to provide balanced load sharing. Failure of one of the slave regulators is detected and the failed regulator replaced by the redundant regulator without interference to the output load current. Failure of the master regulator is detected by steering circuitry within each slave which senses an improper master error signal and transfers control to the reference error amplifier circuity of the slave regulators. Diagnosis of the error conditions is provided by logical analysis of output currents.

Abstract: A switching regulator designed for high power high current transfer is adapted for reducing leakage inductance and heat dissipation. The switching regulator comprises a transformer/receiver assembly utilizing a planar winding configuration in the transformer. The planar secondary winding is a short, large area thermo-path interface for heat dissipation in a cooling medium.

Abstract: An improved connector assembly includes a resistor coated guide pin to facilitate coupling or decoupling a circuit card to a circuit board. A first embodiment of the pin configuration comprises a single taper pin for eliminating current surges during insertion of the pin into its associated plug. A second embodiment of the pin configuration comprises a dual taper pin having two zones of resistance for also eliminating the spark and associated high frequency noise resulting from pin insertion into or removal from the connector assembly.

Abstract: A graphics display apparatus includes a raster-scanned CRT refreshed from a bit-for-pel refresh buffer loaded with bit patterns by a microprocessor corresponding to a desired image. To display shaded areas, additional control logic draws an outline of the area in an auxiliary memory, preferably using Bresenham's Algorithm, according to specified rules. Edge filling logic consisting of EXCLUSIVE-OR gates is used to draw the filled area in the refresh buffer as the outline is read from the auxiliary memory into the refresh buffer. This hardware assistance by the control logic and edge fill logic to the microprocessor enables complex areas to be drawn and filled without unduly degrading the performance of the microprocessor.

Abstract: The invention provides a display apparatus for producing a color image in which the color of each picture element is defined by the intensities of component red, blue and green primaries and is coded as a binary number having r bits defining 2.sup.r intensity levels for red, g bits defining 2.sup.g intensity levels for green, and b bits defining 2.sup.b intensity levels for blue, where g.ltoreq.7, (g-r)=1 or 2, and (g-b)=2. In a particularly advantageous embodiment of the invention the image has a resolution of substantially 4 pels per mm or greater, and g.ltoreq.4.The invention also includes a method of coding a color image as defined above.

Abstract: In an interactive graphics display system in which pels in a frame buffer are mapped to the display screen of a raster display device, a method of automatically highlighting and de-highlighting graphic segments as a cursor is moved across the display screen comprises sampling a locator device at successive points in time to generate a screen cursor at corresponding positions on the screen, examining pels in the frame buffer along a line which extends from the pel corresponding to the previous cursor position to the pel corresponding to the current cursor position to determine whether a pel is "on" along the line, automatically performing a correlate operation in respect of the "on" pel (if any) to identify the graphic segment associated with that pel, and highlighting the segment so identified, any highlighted segment being de-highlighted prior to highlighting a different segment.

Abstract: A dot pattern source image stored in a pattern memory is moved to a specified location in the pattern memory in an angle of n.times.90.degree. (n=0, 1, 2, or 3) with respect to the source image. First, area definition is made for a rectangular source area including the source image to be moved and a rectangular destination area where the source area is to be positioned after the move processing. Then, the positions of four sides of the source and destination areas are compared to determine, for each side, whether there is a processable side region which is included in the destination area but not included in the source area. When such a processable side region is found along one side, the image data in a corresponding region of the source area is moved to the processable side region with a specified angle relative to the source image data.

Abstract: Primary and secondary data save areas are established in a volatile memory (CMOS) which is backed up with a battery. The same predetermined data are stored in the primary and secondary data areas together with check sum. At a power on time, the data of the primary area are added together and the data of the secondary area are added together. When both of results of the addition are equal to the check sum, no error is detected. When only one of results of addition is different from the check sum, an intermittent error is detected. When both of results of addition are different from the check sum, battery exhausted condition is detected. If the intermittent error is detected, data of one area whose result of addition is equal to the check sum are copied to other area whose result addition is different from the check sum.

Abstract: A display system is disclosed comprising a processor, a plasma panel subassembly including generally orthogonally related arrays of conductors and drive circuits for the same, and a read-write memory for storing the image data provided by the processor and delivering drive information to the panel subassembly. Control logic provides arbitration for time sharing the operation of the memory between communication with the processor and with the panel subassembly, storage of modified data tags means associated with the memory operation, and means under the control of the modified data tag means to control update erase and write operations of the panel subassembly on an as-needed individual pel line basis.

Abstract: A test system of this invention is capable of distinguishing interface circuit trouble from keyboard trouble. For diagnosis, an inhibit signal is generated to supply a test clock signal to an output shift register and an input shift register of the interface circuit instead of a clock signal generated from the keyboard, and test data are loaded into the output shift register. If the test data are transferred from the output shift register to the input shift register correctly, it is detected that the interface circuit does not have trouble.