Abstract: A method includes compressing control patterns describing values required at the control signals of blocking logic gates, by linear feedback shift register LFSR reseeding; bypassing blocking logic gates for some groups of scan chains that do not capture unknown values in output response of scan test patterns for testing circuits; and reducing numbers of specified bits in densely specified ones of the control patterns for further reducing the size of a seed of the LFSR.

Abstract: A method of generating a dark-RZ pulse in an optical communications system with a dual-arm modulator by setting a direct current bias on the modulator to a specific value such that an output optical power from the modulator achieves a maximum value when the RF signals on the first and second arms of the modulator are off and maintaining the direct current bias at the specific value and applying RF signals to the first and second arms of the modulator and delaying one of the RF signals applied to one of the first and second arms relative to the other of the RF signals such that a dark-RZ pulse is generated with a duty cycle based on the delay.

Abstract: A method of obtaining a resolution-based proof of unsatisfiability using a SAT procedure for a hybrid Boolean constraint problem comprising representing constraints as a combination of clauses and interconnected gates. The proof is obtained as a combination of clauses, circuit gates and gate connectivity constraints sufficient for unsatisfiability.

Abstract: Disclosed is a density evolution algorithm based on a refined definition of node and edge densities for different parts of the code. In particular, density functions ƒV(1)(i) and ƒV(2)(i) of the output edges of the variable nodes with degree i within different codeword regions w1 and we, respectively, are defined and then calculated. Further, density functions ƒC(1)(j) and ƒC(2)(j) of the output edges for check nodes with degree j within codeword regions w1 and we, respectively, are defined and then calculated. Mixture density functions of output check edges connecting variable nodes in the first codeword region and the second codeword region are then calculated to determine an LDPC code design.

Abstract: An encoder includes an outer repetition encoder, an interleaver for permuting encoding from said outer repetition encoder; and an inner encoder for encoding information from the interleaver to provide a repeat zigzag-Hadamard code. In an exemplary embodiment, a common bit of a zigzag-Hadamard segment of encoding from said inner encoder is a repetition of a last parity bit of a previous zigzag-Hadamard segment of encoding from said inner encoder and said common bit is punctured.

Abstract: A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.

Abstract: A feedback link between a receiver and a transmitter in a multiple antenna communication system is used to control the transmission rate and thereby improve system throughput performance.

Abstract: A symbolic disjunctive image computation method for software models which exploits a number of characteristics unique to software models. More particularly, and according to our inventive method, the entire software model is decomposed into a disjunctive set of submodules and a separate set of transition relations are constructed. An image/reachability analysis is performed wherein an original image computation is divided into a set of image computation steps that may be performed on individual submodules, independently from any others. Advantageously, our inventive method exploits variable locality during the decomposition of the original model into the submodules. By formulating this decomposition as a multi-way hypergraph partition problem, we advantageously produce a small set of submodules while simultaneously minimizing the number of live variable in each individual submodule.

Abstract: A lattice space time coding arrangement for transmission systems is disclosed which enables construction of lattice space time codes with improved error rate performance for arbitrary receiver structures.

Abstract: A multipath routing architecture for large data transfers is disclosed. The architecture employs an overlay network that provides diverse paths for packets from communicating end hosts to utilize as much capacity as available across multiple paths while ensuring network-wide fair allocation of resources across competing data transfers. A set of transit nodes are interposed between the end-hosts and for each end-to-end connection, a transit node can logically operate as an entry gateway, a relay or exit gateway. Packets from the sender enter the entry node and go to the exit node either directly or through one of a plurality of relay nodes. The exit node delivers the packets to the receiver. A multipath congestion control protocol is executed on the entry node to harness network capacity for large data transfers.

Abstract: Implementations of the present principles are directed to test output compaction arrangements and a methods of generating control patterns for unknown blocking. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to balance the number of specified bits in the control patterns across test patterns.

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract: An information retrieval architecture for performing a multi-dimensional search for a lookup value associated with a set of input values, the set of input values organized into one or more fields, the information retrieval architecture including a plurality of classification modules, each classification module storing the lookup values, each lookup value being associated with a set of input values; and a preprocessing module which receives a set of input values and selectively limits search of the plurality of classification modules to a subset of the classification modules.

Abstract: A detection system and method are disclosed which uses sequential Monte Carlo techniques in a multiple-input multiple-output system. The detection system and method samples a first and second component of the modulation symbols separately, thereby reducing the number of symbol candidates and the computational complexity of the system.

Abstract: A precoding technique is herein disclosed for a spread-spectrum transmission system which advantageously addresses intersymbol interference along with multiuser and interchip interference.

Abstract: A method and system usable in sensor networks for handling memory faults is disclosed. In order to protect the operating system of a sensor node, coarse-grained memory protection is provided by creating and enforcing an application fault domain in the data memory address space of the sensor node. The data memory accessed by the application modules is restricted to the region (which defines the application fault domain) within the data memory address space. The application modules are prevented from accessing memory outside the application fault domain through software-based run-time checks. The state belonging to the operations system is maintained outside of the application fault domain, and is thus protected from memory corruption from any application module. In order to ensure that an application module does not operate on a corrupted state, fine-grained error detection and recovery is provided within the application fault domain.

Abstract: A method and apparatus is disclosed whereby the scheduling of network transmissions in a wireless backhaul network is determined using a cross-layer optimization algorithm. In a first embodiment, the algorithm assumes a good MAC layer transmit schedule has been provided and computes optimal network layer routes as well as transmit beam patterns and transmit powers in a semi-distributed manner. According to this embodiment, the optimization goal is the throughput from each access point, or node in the network, to the core network. In another embodiment, an independent set of transmitting nodes is determined at the MAC layer in a way such that no link in the set interferes with another link and no link is scheduled to transmit and receive at the same time. According to this embodiment, a column generation algorithm is used to find a maximal weighted independent set and to achieve optimal network transmission throughput.

Abstract: A training-based transmission technique for multiple-antenna communication systems is disclosed herein where the transmitted symbols are a superposition of the training symbols and the data symbols.

Abstract: A method and apparatus for medium access control in a wireless ad hoc network is disclosed that takes advantage of physical layer properties to jointly and collectively optimize in a distributed fashion transmission parameters such as beam-patterns and transmit powers of all active links in the network. To resolve signal transmission contention, each potential link is associated with a persistence parameter and the persistence parameter is adapted locally, with no central control, to provide medium access for transmissions. Where a node contending for a transmission slot is unable to optimize its transmission parameters due to an invalidity condition or infeasibility condition, the persistence parameter is updated, preferably so as to reduce the probability of such conditions.