Abstract: A method of converting interlaced video to progressive video can include a series of steps. The method can include receiving a video signal representative of at least one picture and determining whether the picture is progressive. If the picture is progressive, a vertical synchronization signal is modified to create an association with a first field of the picture. Accordingly, a progressive video signal can be converted to an interlaced video signal associated with the vertical synchronization signal and the interlaced video signal can then be converted to a progressive video signal in correspondence with modifications made to the vertical synchronization signal.

Abstract: The present invention relates to a method for processing video signals for display on a display panel comprising a matrix array of cells which could only be “ON” or “OFF”, wherein the time duration of a video field is divided into N sub-fields during which the cells can be activated, each sub-field comprising at least an addressing period and a sustaining period, the duration of which corresponding to the weight associated with said sub-field, said method comprising at least a priming period, characterized in that the position of the priming period is determined as follows: determination of a sustain threshold value D for a given addressing speed and panel technology, calculation of the number of sustain pulses in each sub-field n, n being such that 1?n?N, if the number of sustain pulses is above or equal to D, addition of a priming pulse before at least the sub-field n+1. This method is mainly applicable to plasma display panel.

Abstract: An FM broadcast transmitter transmits a broadcast signal having a carrier at a broadcast frequency and sidebands, able to be transmitted at full power, within a transmission band-width around the carrier. It includes a source of a modulated FM stereo signal having a carrier at the broadcast frequency and having sidebands with a bandwidth less than the transmission bandwidth representing a stereo signal. It also includes a source of a modulated IBOC signal, having carrier pulses spaced relative to each other to represent the IBOC digital data signal encoded as a variable pulse width encoded signal, and a bandwidth within the transmission bandwidth not overlapping the FM stereo signal sidebands. A signal combiner combines the modulated FM stereo signal and the modulated IBOC signal to form the broadcast signal.

Abstract: A focusing unit for a cathode ray tube comprises a plurality of permanent magnets, each having a longitudinal axis, and a plurality of coils. A form holds the magnets in a first annular array at substantially equally spaced intervals in which the magnet axes are substantially parallel to a longitudinal axis defined by the first annular array and holds the coils in a second annular array at positions spaced angularly between the magnets. Annular flanges of high magnetic permeability are disposed over longitudinally opposite ends of the magnets. At least one annular winding is disposed substantially adjacent to and inwardly from the first array of the magnets. In one embodiment, the coils are helical coils disposed in substantial circumferential alignment with the first annular array of the magnets. The helical coils each having a substantially is radially aligned longitudinal axis.

Abstract: An apparatus for distinguishing a wanted signal in a binary signal sequence having both wanted signals and interference signals includes the step of generating a correction value which has a first value to indicate a wanted binary signal and a second value to indicate a binary interference signal. The wanted signal has a preselected maximum number of bits. A first counter counts the bits of the binary signal sequence and changes the correction value from the first value to the second value when the preselected maximum is exceeded. The correction value is reset to the first value when the temporal spacing between two occurrences of excesses of the preselected maximum number exceeds a predetermined spacing.

Abstract: Two windings of a flyback transformer in a horizontal deflection circuit are inductively coupled with opposite polarity to a source of horizontal rate retrace pulses. The windings have a common junction coupled to ground. A circuit energized by the retrace pulses generates modulated currents of opposite polarity. Conduction of each current is controlled by a switch circuit including a semiconductor switch and two diodes. The switch circuits are coupled to one another at a junction, and the junction is coupled to an energy storage capacitance. One of the diodes conducts positively valued portions of the respective current through the energy storage capacitance and the other of the diodes conducts negatively valued portions of the respective current through the semiconductor switch. Each semiconductor switch is a current discharge path.

Abstract: A horizontal deflection system comprises a horizontal deflection yoke and a resonant retrace circuit coupled to the yoke and to a switched energy source for generating a horizontal deflection current in the yoke. A diode modulator is coupled to the resonant retrace circuit. A control circuit operable in a switched mode supplies a control signal to the diode modulator for modifying the deflection current to correct for side pincushion distortion. A transformer has a first winding coupled to the diode modulator and to the control circuit for recovering energy from the diode modulator. The transformer has a second winding for receiving the recovered energy from the first winding. A diode clamp is coupled to the second winding and to a load driven by a voltage source at a first voltage level, for transferring the recovered energy from the second winding to the load.

Abstract: A standby/run power supply and control circuit for a television apparatus comprises first and second sources of DC voltage, one of which is unswitched and available during a standby mode of operation and the other one of which is switched and available only during a run mode operation. A voltage regulator has an input coupled to both DC sources and has an output for supplying a regulated DC voltage at a first power level during the standby mode and at a second power level during the run mode. A first control circuit, such as a CMOS integrated circuit, is coupled to the regulated voltage output and operable in both the standby and run modes. A second control circuit, such as a second CMOS integrated circuit, is interconnected with the first control circuit, for example by a common control bus. The second control circuit is also coupled to the regulated voltage output, but is operable only during the run mode.