Abstract: A method for fabricating a patterning mask is disclosed in which a membrane layer is deposited on a first surface of a substrate. Patterned and unpatterned portions of the substrate are then defined on a second surface of the substrate. A majority of the thickness of substrate in the unpatterned portions is then dry etched to partially define a strut having sidewalls that are substantially perpendicular to the first surface. Wet etching is then performed to etch through the remaining thickness of the substrate to expose the bottom surface of the membrane layer and completely define the strut. Scattering elements may then be formed over the membrane layer. In one embodiment, the substrate is silicon and has a (110) orientation and an edge of the silicon struts is aligned to a {111} plane. In another embodiment, an edge of the silicon struts is aligned to a {221} plane.

Abstract: An ASIC design methodology in which portions of the ASIC are implemented in silicon or other suitable semiconductor technology at an early stage in the design flow through the use of a series of interim devices. The invention provides a method in which additional portions or subsystems of the integrated circuit are incorporated into successive versions of the interim device. In this manner, the invention provides for the gradual incorporation of a plurality of architectural subsystems into the integrated device such that the synthesis and verification of each iteration is broken into manageable pieces. In the preferred embodiment, this design method is facilitated by incorporating a programmable portion into the design flow of each interim device such that each interim device includes a custom portion into which the subsystems that have been implemented in silicon are fabricated and a programmable portion.

Abstract: A semiconductor wafer comprising a single crystalline lattice suitable for use in the manufacture of integrated circuits, namely computer chips and dies, wherein a diameter of the wafer is greater than approximately 150 millimeters and wherein the wafer includes a first hole extending through the wafer. The hole is adapted to facilitate handling of the wafer without directly contacting a surface of the wafer. The wafer preferably includes a primary flat and the first hole includes a flat side having a predetermined and known orientation with respect to the primary flat of the wafer. In one embodiment, the wafer further includes a guide hole formed near the first hole such that the center-points of the first hole and the guide hole are oriented with a predetermined and known orientation with respect to the primary flat of the wafer.

Abstract: A synchronous converter including a control module including a pulse generator configured to produce a pulse. An input port suitable for receiving an input voltage from a voltage source, is couple to a first conversion stage of the converter. The first conversion stage preferably includes a first pair of transistors, a first stage capacitor, and a first winding of a coupled inductor. The first pair of transistors are preferably driven by the control module pulse generator such that the first conversion stage is coupled to the input port during the first interval of the pulse and isolated from the input port during the second interval of the pulse and the gain of the first conversion stage is approximately equal to the duty cycle of the pulse. The converter further includes a second conversion stage preferably including a second pair of transistors, a second stage capacitor, and a second winding of the coupled inductor.

Abstract: A semiconductor process including forming a gate dielectric on a semiconductor substrate. First and second conductive gates are then formed on the gate dielectric. The conductive gates are aligned over respective channel regions of the substrate. The channel regions are laterally displaced between respective pairs of source/drain regions. A first interlevel dielectric is then deposited on the substrate and source/drain vias are then formed in the interlevel dielectric. The source/drain vias terminate on the pairs of source/drain regions. Thereafter, a source/drain impurity is introduced into the source/drain regions to form source/drain structures. A conductivity type of the source/drain structures is opposite a conductivity type of the field region. The first interlevel dielectric substantially prevents the source/drain impurity from entering the field region of the semiconductor substrate.

Abstract: An air duct structure for use in cooling a circuit card comprised of a printed circuit board to which an integrated circuit is connected. The air duct structure includes an air duct cover and a spring. The air duct cover includes a major panel that is sized or dimensioned to substantially cover the circuit card. First and second side panels extending substantially perpendicularly from opposing ends of the major panel to form a bracket. A depth of the bracket is suitable for receiving the circuit card and a heatsink positioned in close contact with the integrated circuit. When the circuit card and the heatsink are suitably received within the air duct cover, the air duct cover and the printed circuit board define an air duct within which the heatsink resides. The spring is attached to an interior surface of the major panel.