Abstract: A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spacer regions are formed on sides of the sidewall spacer regions. Upper regions of the gate structure and the sidewall spacer regions are silicided. Portions of source and drain extension regions in the semiconductor substrate adjacent the gate structure are also silicided.

Abstract: An apparatus and method for an electrodeposition or electroetching system. A thin metal film is deposited or etched by electrical current through an electrolytic bath flowing toward and in contact with a target on which the film is disposed. Uniformity of deposition or etching is promoted, particularly at the edge of the target film, by baffle and shield members through which the bath passes as it flows toward the target. The baffle has a plurality of openings disposed to control the localized current flow across the cross section of the workpiece/wafer. Disposed near the edge of the target, the shield member shapes the potential field and the current line so that it is uniform.

Abstract: A semiconductor memory device including at least three different types of memory cell structures. The types include an NVRAM cell structure, an FERAM cell structure, a DRAM cell structure, and an SRAM cell structure. The cell structures are disposed on the same substrate.

Abstract: A process for forming a planar silicon-on-insulator (SOI) substrate comprising a patterned SOI region and a bulk region, wherein the substrate is free of transitional defects. The process comprises removing the transitional defects by creating a self-aligned trench adjacent the SOI region between the SOI region and the bulk region.

Abstract: A process for fabricating a tapered trench on a silicon substrate. The process comprises the steps of forming an initial trench in the substrate and implanting nitrogen ions on the initial trench side walls. More nitrogen ions are implanted adjacent the exposed surface of the substrate than adjacent the trench bottom. Finally, the initial trench side walls are oxidized to create the tapered shape.

Abstract: A method of self-programmable Built In Self Test (BIST) for a memory (e.g., Dynamic Random Access Memory (DRAM)). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.

Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.

Abstract: An electrodeposition apparatus for depositing material on a surface of a substrate. The electrodeposition apparatus includes at least one contact for laterally contacting the substrate and providing electrical connection to the substrate. The at least one contact does not obscure the surface of the substrate to be plated. A voltage source is connected to the at least one contact.

Abstract: A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.

Abstract: A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown in top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.

Abstract: A process for making a capacitor for a silicon-on-insulator (SOI) structure. The SOI structure has a p-type silicon base layer, a buried oxide layer, a silicon layer, and an n+ layer formed within a portion of the p-type silicon base layer. The process comprises the steps of forming a buried oxide layer and a silicon layer in the p-type silicon base layer, forming an n+ layer in a portion of the p-type silicon base layer, and forming electrically conductive paths to the p-type silicon base layer and the n+ layer extending through the buried oxide and silicon layers.

Abstract: A planar silicon-on-insulator (SOI) structure and a process for fabricating the structure. The SOI structure has a silicon wafer, an oxide layer, and a silicon layer. Trenches are formed, extending from the top surface of the structure to the silicon wafer, and are filled with a semiconductor. The trenches have a top, a bottom, and side walls. The side walls have side-wall silicon portions. The side-wall silicon portions of the trench side walls are covered by trench side-wall oxide layers. A protective side wall extends over the trench side walls and trench side-wall oxide layers from the trench top to the trench bottom.