Abstract: A field effect transistor and method for making same in which a first source/drain impurity distribution is located at a first depth below an upper surface of the semiconductor substrate and a second source/drain impurity distribution is located at a second depth below the upper surface. In a presently preferred embodiment, the first depth is greater than the second depth such that the transistor includes a channel region having a vertical component. The channel region extends from the first source/drain impurity distribution to the second source/drain impurity distribution. The field effect transistor further includes a gate dielectric which is in contact with the channel region and a conductive gate structure in contact with the gate dielectric layer. The vertical component of the transistor channel length can be accurately controlled with plasma etch techniques.

Abstract: An integrated circuit transistor vertically oriented along a side wall of a shallow trench formed in a semiconductor substrate. The transistor includes a semiconductor substrate, preferably comprised of silicon, into which a shallow transistor trench has been formed. A trench floor of the transistor trench is vertically displaced below the upper surface of the semiconductor substrate by a trench depth. The transistor further includes a drain impurity distribution having a peak concentration that is vertically displaced a drain depth below the semiconductor substrate upper surface. The drain depth is less than the trench depth. The transistor further includes a channel impurity distribution having a peak concentration vertically displaced a channel depth below the substrate upper surface. The channel depth is greater than the drain depth, but less than the trench depth. The drain impurity distribution and the channel impurity distribution extend laterally to a first side wall of the transistor trench.