Abstract: An improved printed circuit board (PCB) for interconnecting integrated circuit devices includes a lead frame sandwiched between two multilayer substrates. Integrated circuit devices are mounted on the top of the upper substrate and on the bottom of the lower substrate to provide increased packaging density. Thus, according to the present invention, it is possible to provide a simply constructed electronic component mounting PCB which facilitates the design of circuits, and affords excellent connection reliability, which can readily form a heat radiating structure, and in which the thermal matching with the electronic component is excellent.

Abstract: Apparatus, and an accompanying method, for accurately detecting bit-error densities in a serial bit stream and particularly relatively low bit-error densities. Specifically, detected bit-errors are synchronized to a bit clock using a error retiming circuit (130). Subsequently, the bit-errors are counted using a first counter (165) during a pre-defined measurement interval, equivalent to a specified number of bit clock cycles. A second counter (205) establishes the measurement interval by counting the specified number of bit clock pulses. Whenever the first counter attains a count larger than a pre-defined count, during the measurement interval, an output (alarm) signal is generated to indicate that a pre-defined threshold error density has been exceeded. Both the first and second counters are then reset at the conclusion of the measurement interval, and so on for successive measurement intervals.

Abstract: A thermal cut-off resistor that has an elongated thermal cut-off fuse; a wire-shaped resistor that is tightly coiled around the fuse, said resistor being physically connected to the fuse so that the fuse and the resistor are in an electrical series arrangement; and an electrically-insulated heat-resistant casing that contains the fuse and resistor therein and enables the fuse and the resistor to be secured and electrically connected to respective electrical contacts formed on a printed circuit board, the profile of the casing being approximately the width of the fuse.

Abstract: The relay comprises a flat base, a motor unit mounted on the base, an armature arranged on one end of the motor unit to actuate a contact arrangement fastened on the base at the other end of the motor unit. The movement of the armature upon energization or de-energization of the motor unit is transferred to the contact arrangement by means of a pusher arranged above the motor unit. The pusher is clamped to the armature by means of a multi-functional retainer spring which serves also for fastening the armature to a frame and for biasing the armature into its rest position. The motor unit is inserted with terminals and bobbin posts into oblong holes of the base so as to be displaceable in an actuating direction for adjusting a contact gap or overtravel during assembly of the relay and before securing the motor unit to the base.

Abstract: An electromagnetic relay to be used in applications such as DC motor reversing. The relay consists of two electromagnetic devices in a single enclosure with contacts configured in a so-called "H-bridge" circuit. Each of the devices has a movable contact element, while both devices have a common pair of normally closed and normally open stationary contact elements. Both electromagnetic devices have coil bobbins which are preferably identical in shape and are locked together by means of the common stationary contact elements without a need of additional fastening means. In this manner, the number of parts is minimized and the amount of adjustment required is reduced.

Abstract: An integrated cascaded optical phase modulator for providing linearized complementary modulated light output signals consists of the successive cascade of a first phase modulator stage, first fixed optical coupler, second phase modulator stage, and second fixed optical coupler Rf modulating signals applied to each phase modulator stage are adjusted in amplitude, for compensating for errors in the coupling angles of the first and second optical couplers. The levels of DC bias voltages applied to each phase modulator stage are adjusted for compensating for asymmetric phase modulation.

Abstract: A system for determining the presence or absence of data on one or more data lines including a flip-flop for each data line with the output of each flip-flop connected to a NAND gate. The NAND gate is connected through an OR gate to two output flip-flops in series. The logic of the system is such that the output of the second of the two output flip-flops provides a signal level which is high or low depending on whether data is present on all of the data lines or one or more lines has no data.

Abstract: A rocker actuator switch having a frame which has a first projection extending therefrom which passes through a yoke portion of a rocker actuator that moves between on and off positions. The rocker actuator is pivotally connected to the frame by a snapping arrangement whereby a second frame projection is guided and slides along a flexible cantilevered beam, which is disposed in a sidewall of the rocker actuator, until the second projection enters a partial circular cutout in the sidewall of the rocker actuator. Upon entering the cutout, the flexible beam retains the second projection in the cutout where it is free to pivot.

Abstract: A process for generating a logic netlist suitable for a logic simulator model from a data or netlist representation (11) of a circuit of transistors and resistors in either emitter coupled logic or current mode logic technology. The logic netlist is formed to serve as a logic simulation model having logic elements structured and patterned to follow the circuit representation at the transistor level, most commonly known as a netlist, which includes the resistors and the overall circuit interconnection. The logic extraction process (1.0, 2.0) identifies active and passive circuit elements connected according to prescribed criteria to eliminate elements which do not contribute to logic functionality as well as identifying elements essential to providing the logic functionality. A systematic approach keeps track of circuit nodes to enable the appropriate interconnection of logic elements patterned after the physical circuit represented as the netlist.

Abstract: An optical element composed of a single crystal consisting essentially of potassium titanyl phosphate, which is represented by the formula KTiOPO.sub.4 and which is doped with cerium. The optical element has a high optical transmissivity property for radiation from the near-UV to the mid-infrared spectral regions.

Abstract: A data scrambler circuit which adds the SONET polynomial 1+X.sup.6 +X.sup.7 to data in a parallel format to thereby reduce circuitry clock rates to one-eighth the line rate, which reduces power consumption and simplifies timing constraints. A circuit embodiment includes a first series of flip-flops connected to generate the polynomial and a second series of flip-flops for holding the generated polynomial. To provide a relatively large window of time for looking at the data, parallel data is obtained by providing a parallel-to-parallel register at the output of a serial-to-parallel register. The parallel data is added to the held polynomial by a series of exclusive OR gates.

Abstract: The gate-source capacitance of a power MOSFET (1) can be protected against positive and negative excess voltages by two integrated Zener diodes (3, 4) the anodes of which are coupled to each other and the cathodes of which are respectively coupled to the gate and source terminals of the power MOSFET. However, when a control voltage is applied, the parasitic bipolar transistor associated with one of the Zener diodes is switched on and prevents the MOSFET from completely switching on. The parasitic bipolar transistor is rendered harmless by the fact that the anode terminal is coupled to a source terminal (S) MOSFET (1) when a gate-source voltage is applied.

Abstract: A data scrambler circuit which adds the SONET polynomial 1+X.sup.6 +X.sup.7 to data in a parallel format to thereby reduce circuitry clock rates to one-eighth the line rate, which reduces power consumption and simplifies timing constraints. A circuit embodiment includes a first series of flip-flops connected to generate the polynomial and a second series of flip-flops for holding the generated polynomial. The parallel data is added to the held polynomial by a series of exclusive OR gates.

Abstract: There is described a 2.times.2 switch matrix which includes four 1.times.1 switch matrix modules. Each 1.times.1 switch matrix module consists of an active power divider switch (APDS), an active power combiner switch (APCS) and an air bridge crossover. Additional APDSs and APCSs are utilized in the matrix to compensate for path length differences between different input to output signal paths thus providing good phase and amplitude tracking. The basic switch matrix modules are utilized to form a 2.times.2 switch matrix whereby two primary input ports can be connected to any one of two primary output ports. The 2.times.2 switch matrix is utilized to formulate larger matrix arrays as N.times.M configuration. Each of the active power divider switches and power combiner switches utilize two separate dual gate FETs which are suitably interconnected, depending upon whether the circuit is to be used as a power combiner or power divider.

Abstract: A Y-branch type first interferometric modulator, and a coupler structure type second interferometric modulator are connected in cascade. The levels of DC bias voltages applied to the first and second interferometric modulators, respectively, are adjusted for maximizing the linearity of a modulated output light signal. The configuration of input and output coupler structures of the second interferometric modulator are predetermined for also contributing to maximizing the linearity of the output signal.

Abstract: A protective circuit for removing power from a load detects the presence of a control signal which causes electrical power to be delivered to a load, for example, via a controlled switching device such as an electromechanical relay or a solid state relay. The protective circuit also detects the presence of voltage across the load, signifying that the controlled switching device is causing power to be supplied to the load. The protective circuit removes power form the load when there is an absence of control signal and there is voltage across the load, indicating a failure of the controlled switching device.

Abstract: A unitary optical fiber splice support and routing guide insuring that at least a minimum bending radius is maintained for the fiber and allowing for a flexible routing pattern which stores on the device a wide range of fiber lengths.

Abstract: A technique of providing numerous distinct conductive patterns on a piezoelectric substrate is accomplished using only two masking apparatus. One masking apparatus defines a common portion or structure for each of the patterns. The second masking apparatus defines numerous distinct patterns, each corresponding to a different alignment position with respect to the common structure already formed on the substrate. One application for this technique is in economic production of coded SAW devices which may serve as coding or decoding devices, filters, or correlators, each of the SAW devices having a different individual code.

Abstract: A frame error detection system for SONET which operates in both the OC-3 and OC-12 modes. The frame detection circuit operates by examining the incoming data bit stream, which is in parallel form, detecting A1 and A2 bytes and if, in the OC-3 mode, three consecutive A1 bytes are received, followed by three A2 bytes, then framing is correct. If one of these bytes is missing, then there is an error in framing. The bytes, as they are received and processed by the system, are stored in a series of flip-flops and the output logic signal therefrom is indicative of the framing condition as to whether it is correct or errored.

Abstract: A bipolar transistor is disclosed including a semiconductor body having a cathode-side surface and an anode-side surface, and at least one insulated gate electrode. The semiconductor body has a central region with a predetermined doping concentration and of a first conductivity type. The central region borders on the cathode-side surface of the semiconductor body. Bordering on the cathode-side surface, at least one gate region is provided which borders on the central region. The gate region is of the second conductivity type and has a higher doping concentration than the central region. In the gate region, a source region is provided which borders on the cathode-side surface. The gate electrode is seated on an insulating layer applied on the cathode-side surface and covers the gate region. Between the anode-side surface and the central region is provided an anode region of the second conductivity type which has a higher doping concentration than the central region.