Patents Represented by Attorney JP & T Group LLP
  • Patent number: 7952386
    Abstract: There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: May 31, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Beom-Ju Shin