Patents Represented by Attorney Jqacqueline J. Garner
  • Patent number: 6087220
    Abstract: A method of forming a floating gate memory array is provided that uses a two step etch process to prevent the formation of unwanted trenches 66 into the semiconductor substrate 26. The process may be accomplished by a first etch which is substantially not selective between silicon and dielectric materials. A second etch process is then used which is highly selective to dielectric materials.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: July 11, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Daty Michael Rogers, Reima T. Laaksonen, Cetin Kaya, Freidoon Mehrad, Men-Chee Chen