Abstract: A system is provided on an Integrated Multiport Repeater (IMR) to monitor the activity of the IMR when the repeater is in minimum mode. Through this system the serial output pin outputs status based upon inputs at two input pin the signal in and the clock signal. In a preferred embodiment there are four different status outputs, partition, loopback/link, Bitrate and SQE/Polarity. This system finds use in low end applications where complex control circuitry is not desired.

Abstract: An output buffer circuit is disclosed that minimizes propagation delay and crowbar current. This circuit receives a data input signal and provides an output signal. This circuit includes a pull-up transistor, a first pull-down transistor, a speed improvement circuit and a crowbar current reduction circuit. The speed improvement circuit comprises an inverter with small propagation delay coupled to a second pull-down transistor which is smaller than the first pull-down transistor. The speed improvement circuit minimizes the propagation delay of the circuit when the data input signals changes from a high logic level to a low logic level by speeding up the initial rate of fall of the output signal due to the fast turning on of the second small pull-down transistor which receives the data input signal quickly through the small-propagation-delay inverter. The crowbar current reduction circuit comprises a first crowbar current reduction transistor which is smaller than the pull-up transistor.

Abstract: An improved circuit topology for implementing level detection and data restoration operations on an input sinusoid. The differential high-frequency level detector and data restoration circuits of the present invention each include a differential input having a pair of circuit nodes for receiving a differential input signal. A slicing offset network is disposed to generate first and second differential signals in response to the differential input signal. The present invention further includes first and second comparators for respectively providing latch set and latch reset signals in response to the first and second offset differential signals. The data restoration circuit of the present invention further includes a latch operative to synthesize a recovered data waveform in accordance with pairs of set and reset signals. Similarly, the inventive level detector includes a latch which utilizes set and reset signals to generate a level detection signal.

Abstract: A system provides for detection of enhanced capabilities of stations on a communications network. A specified pattern of link test pulses are detected and transmitted to provide for the indication of enhanced capabilities. This is particularly useful for determining whether a particular station is in full duplex or half duplex mode without affecting overall network performance.

Abstract: A high speed multiple input NOR gate. In an illustrative embodiment, the invention includes a plurality of pull-down transistors for providing an output signal. A pull-up transistor is coupled to the plurality of pull-down transistors for providing a drive current. A regulator is coupled to the pull-up transistor for regulating the drive current in response to temperature and power supply voltage variation so as to maintain the speed of the output signal during a low-to-high transition of the output signal. In specific implementations, the NOR gate is designed to regulate the output signal so that a high level or a low level thereof is maintained at a predetermined level.

Abstract: A system and method for obtaining the bearing angle of radio frequency is utilized in a direction finding system to determine the signal of interest. The system utilized an adaptive interferometric processor to null out modulation occurring due to commutation between the antenna elements. Through this system the bearing angle can be determined accurately and efficiently.

Abstract: An output buffer circuit is provided which significantly reduces ground/Vcc bounce and glitches of signals provided to an integrated circuit. The circuit includes a plurality of transistors for providing a drive potential at the output of the device. The transistors are coupled such that they increase in size from the input to the output of the output buffer circuit. A control circuit provides control signals for sequentially turning off the transistors from the largest to smallest device thereby substantially reducing the Vcc bounce and glitches of the signals provided to the integrated circuit by the output buffer circuit.

Abstract: A sense amplifier is provided that has improved speed from input to output, particularly during low-to-high transitions on the output and minimizes power consumption. By removing the product term window circuit from the critical node, the overall speed of the amplifier is maximized. In addition, circuitry is included to speed up low-to-high transitions, high-to-low transitions and provide increased noise immunity over temperature variations.