Abstract: A system is described for tracking the position of a light source by mounting two orthogonal triangular interferometric systems on a gimbaled platform. The interferometric systems each provide a carrier frequency signal depending upon their pointing angle with respect to the light source. These carrier signal frequencies provide the error signals for the X and Y axis drives of the platform.

Abstract: A vector voltmeter for measuring the amplitude and phase difference between two signals. A first signal is fed to a power divider in which one of its outputs is measured with a power detector and the other output is fed to a second divider, each output thereof being fed one each to a third and fourth power divider. The second signal is fed to a fifth power divider in which one of its outputs is measured by a second power detector and the other output of the fifth divider is fed to a hybrid circuit having quadrature outputs, one of which is fed to the third power divider whose output is measured by a third power detector and the other quadrature output is fed to the fourth power divider whose output is measured by a fourth power detector. The four power detectors are connected to two differential amplifiers which drive the X and Y axis of an oscilloscope.

Abstract: An apparatus for testing an incremental shaft encoder in which the encoder is placed upon a rate table together with a gyroscope to permit coincident rotation. Every time the shaft of the incremental shaft encoder turns through a complete cycle, the leading edges of a square wave output generated by the encoder, start and stop a counter which is fed by a frequency signal derived from the rotating gyroscope through a voltage-to-frequency converter. The counter output then is applied to a printer.

Abstract: A hybrid sample data filter system using quantized data of an analog signal obtained from a delta modulator. A shift register having N preselected taps is fed by the delta modulator. Each of the N taps are fed to a series of AND gates corresponding to the R stages of a coefficient counter and between the stages of the coefficient counter and the AND gates are coefficient setting switches set in accordance with the predetermined weighting of the output taps of the shift register. A ring counter having N stages is also fed to the AND gates for time mutliplexing with each of the stages of the ring counter feeding those AND gates that are fed by the corresponding tap of the shift register. Each of the AND gates fed by the same stage of the R stage coefficient counter is combined in one of a series of N-input OR gates, the output of which is fed to a R-input digital-to-analog converter. A demodulating filter is then connected to the output of the digital-to-analog filter.

Abstract: A low height, high efficiency antenna system in which a plurality of radiating elements are spaced to induce mutual radiation resistance in each other and the elements radiate using constant current which is obtained with a parallel folded element that receives the current prior to the radiating element, and since the current is moving in opposite directions in the folded element all but the constant current component is cancelled. The edge of the supporting tower can be used as one or two legs of the folded element.

Abstract: A digital analyzer for a laser velocimeter which compresses data into groups for a histogram display. A data processor containing the velocimeter information is fed through a multiplexer to a memory which is controlled by a data interrupt circuit that is fed by a two-phase clock. One phase of the clock pulses an address counter which feeds the multiplexer and a first digital-to-analog converter that controls the x-drive of a cathode ray tube. The data processor also has an output fed to a full adder and then fed back to the memory with the same output being fed to a storage register followed by a second digital-to-analog converter that controls the y-drive of the cathode ray tube.

Abstract: A two's complement subtractor using a one bit full adder for the most significant bit. A series of arithmetic logic units are fed by the respective binary bits to be subtracted with the logic units effecting internal two's complementing of the subtrahend thereby permitting adding to the minuend. The most significant input bits are in addition fed to a one bit full adder together with the carry in bit from the last arithmetic logic unit of the series. The one bit full adder outputs the most significant bit or the sign resulting from the subtraction and this adder can have either internal inversion of the subtrahend or an inverter can precede the subtrahend input.

Abstract: An antenna system in which a conical shaped metallic radome has a surface composed of a periodic array of radiating slot elements. Each slot element has three arms connected to each other and extending radially outward with the angular distance between adjacent arms equal to 120.degree.. The slot elements are aligned in order to have each of the arms in an element parallel to an arm in an adjacent element forming a uniform periodic array.

Abstract: A regulating digital power supply in which an error detector compares a reference signal voltage with an unknown loop signal voltage and upon being strobed the error detector outputs a signal depending upon the relative magnitude of the two input signals. This output signal controls the direction of count of an up/down counter that counts clock pulses. At appropriate intervals as controlled by the clock, the contents of the up/down counter are transferred to a down counter upon a command signal which also sets a flip-flop. When the down counter reaches zero and overflows it emits a signal that resets the flip-flop, the output thereof being a pulsewidth modulated regulated power supply. The flip-flop also controls a switch to a power source that is rectified and filtered and then fed back to the error detector comparator, thereby completing the loop.

Abstract: Threshold count pulses, the number of which being proportional to the slope of an impedance curve of a radiating antenna in an RF detection system, are counted in a first counter and, upon receipt of a read pulse representing a threshold of impedance, are transferred to a memory counter while the read pulse delayed resets the first counter. The values in these two counters are compared in a first comparator which emits a pulse if the value of the first counter is greater than that of the memory counter and in the absence of these pulses a sequencer emits a signal indicating a target is moving outwardly. The threshold count pulses also feed an AND gate together with pulses from the first comparator with the AND gate output being fed to a third counter. The third counter is compared in a second comparator which emits a pulse upon equality indicating the target has approached an inner boundary. The third counter is reset with delayed read pulses.

Abstract: A sample data filter using a delta modulator to feed a shift register of which selected outputs are pulsewidth weighted. Each of the coefficient multipliers include a flip-flop fed by one of the taps of the shift register and triggered by a clock. A synchronous counter, common to each of the multipliers, is fed to a NAND gate that clears the flip-flop. Interposed between the counter and the NAND gate are a series of switches, one for each stage of the counter. The flip-flop controls a switch to a source of reference voltage and the output of this switch controlled voltage from each of the multipliers is summed and fed to a demodulator.

Abstract: A system for trim balancing a rotating engine by remote control. A pair of concentric counterweight discs each having lightening holes to render the discs weighted to one side and these unbalanced discs are positioned in the spinning hub of a rotating engine. Control signals are transmitted to activate a pair of servo motors each controlling the angular position of one counterweight disc. The angular position of the discs with respect to each other can be controlled as well as the angular position of the pair of discs taken together with respect to the rotating engine.

Abstract: A perspective display of a runway is obtained on an aircraft by transmitting signals from selected marker positions about the runway. A plurality of sensors are positioned on the aircraft with each sensor being compared to a reference frequency. The comparisons are made measuring the accumulated phase difference during a given time with these phase differences being equivalent to distances which are then fed to a computer and displayed as a perspective view.

Abstract: A perspective display of a runway is obtained on an aircraft by sequentially transmitting signals from selected marker positions about the runway. A plurality of sensors are positioned on the aircraft with a first sensor being compared to a reference frequency and the other sensors being compared each with the first sensor. The comparisons are made measuring the accumulated phase difference during a given time with these phase differences being equivalent to distances which are then fed to a computer and displayed as a perspective view.

Abstract: A phase stable limiter in the form of an emitter coupled amplifier. First and second parallel connected transistors have their emitters resistively coupled with the input terminal at the base of the first transistor and an output terminal at the collector of the second transistor. Another resistor is connected to the resistively connected emitters and to this resistor is connected a grounded variable capacitor. An inductor is connected between the base and the collector of the second transistor.

Abstract: A system for varying the function of a keyboard using a plurality of status keys to select a function. The status keys form a binary which are decoded in a first word decoder forming a single word which are fed to a plurality of binary decoders one each associated with one of the information keys on the keyboard for controlling the readout thereof. The information keys are also switches that activate a word encoder for producing a final output. A comparator gate can be interposed between the word encoder and the selection switches of the information keys, the gate being enabled by the first word decoder. The decoded word originating from the status keys also feed a segment decoder which activates segments surrounding selected information key elements.