Abstract: A data processing system having register controllable processor speed includes a central processor (110) which operates at a selectable address bus clock speed (122) and subsystem components (115) also having selectable speeds. Subsystem clock provision conductors (124) independently provide a selectable subsystem clock speed for each of the subsystem components. Addressable registers (200, 250, 300) store a plurality of optimum address bus clock speed and subsystem clock speed values. A selector circuit (137, 138) reads a first addressable register to provide the optimum speed value for use as the selectable address bus clock speed of the central processor and reads a second addressable register to provide the optimum speed value for use as the selectable subsystem clock speed of a first subsystem clock component.