Abstract: An interface for an electronic device being coupled to an external device is provided. The interface includes a configurable hardware interface and a storage component for storing a bitstream that configures the configurable hardware interface to implement the driver of the external device. Specifically, the storage component can store one or more bitstreams that correspond to known drivers that can operate with the electronic device. The configurable hardware interface can include a programmable logic device (PLD), a memory, a control interface for controlling the PLD and the memory, and a synchronous communication interface for receiving information from the external device and enabling the control interface. The memory can list the device drivers (i.e. bitstreams) stored in the storage component and their respective addresses. The interface provides the advantage of storing any number of drivers in the device, thereby significantly reducing the time for the two devices to establish communication.

Abstract: A glitchless T length pulse is generated by coupling a trigger signal and the latched output of a counter. The trigger signal initiates the start of the T length pulse, and the latched output of the counter initiates the end of the T length pulse after counting up a duration of T from a number of clock cycles of a clock signal. Latching the output of the counter prior to terminating the T length pulse eliminates glitches. Accuracy of the count determining the length of the T length pulse may be increased by latching the trigger signal with the clock signal to generated a synchronized trigger signal, and using the synchronized trigger signal to initiate the T length pulse.

Abstract: An active inductance circuit for ESD parasitic cancellation is described. A feedback circuit on a transconductance amplifier is utilized to transform and reflect the impedance of an active inductor to minimize effects of parasitics produced by ESD circuitry. The active inductance circuit may be programmably implemented, allowing tunable component values.

Abstract: A method of configuring FPGAs for reconfigurable computing comprises a software environment for reconfigurable coprocessor applications. This environment comprises a standard high level language compiler (i.e. Java) and a set of libraries. The FPGA is configured directly from a host processor, configuration, reconfiguration and host run-time operation being supported in a single piece of code. Design compile times on the order of seconds and built-in support for parameterized cells are significant features of the inventive method.

Abstract: A clock routing circuit is coupled to receive a primary clock signal, a secondary clock signal, and a select signal, all of which may be asynchronous with respect to one another. When the select signal is in a first state, the clock routing circuit passes the primary clock signal as an output clock signal. At time TA, the select signal transitions to a second state, thereby indicating that the secondary clock signal should be routed as the output clock signal. The first clock signal is prevented from being routed as the output clock signal at time TB, wherein time TB is the first time that the first clock signal has a predetermined logic state after time TA. The output clock signal is held at the predetermined logic state at time TB. The second clock signal is then routed as the output clock signal the first time that the second clock signal transitions to the predetermined logic state after time TB.

Abstract: The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAS. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM references or includes one or more floorplanners each of which may employ one or more placement algorithms. Such placement algorithms might include, for example: a linear ordering algorithm that places datapath logic bitwise in a regular linear pattern; a rectangular mesh algorithm that implements memory in a grid pattern in distributed RAM; a columnar algorithm for counters and other arithmetic logic; or a simulated annealing algorithm for random logic such as control logic. Therefore, a design including more than one SIM can utilize a plurality of placement algorithms at the same or different levels of hierarchy.

Abstract: The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters that may, for example, include the required timing, data width, number of taps for a FIR filter, and so forth. SIMs are called “self implementing” because they encapsulate much of their own implementation information, including mapping, placement, and (optionally) routing information. Therefore, implementing a SIM-based design is significantly faster than with traditional modules, since much of the implementation is already complete and incorporated in the SIM.

Abstract: A negative voltage detector is disclosed wherein a resistor divider circuit is used to translate a negative voltage into a standard CMOS logic low or logic high value. The small area consumed by the negative voltage divider of the present invention allows multiple device placement within a logic device without the consumption of much area on the logic device. Additionally, the multiple devices placed may detect different negative voltage thresholds with a simple tuning of device components.

Abstract: A shift register system is disclosed wherein shift registers buffering memory data perform shift operations in response to a set of sub-clock signals. The set of sub-clock signals comprise nested sub-clock signals having non-overlapping transitions formed from a system clock signal or power on reset signal. Each shift register (or bank of shift registers) responds to a different sub-clock signal. As a result, shift operations are spread out over a period of time rather than occurring simultaneously. Thus, the current drawn during each shift operation is similarly spread out over a period of time. The maximum current drawn during any one shift operation is inversely proportional to the number of non-overlapping sub-clock signal. Therefore, the maximum current drawn (i.e., current spike) drawn during memory operations is minimized.

Abstract: The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM automatically places and interconnects child SIMs in a mesh pattern. The mesh is a 2-dimensional object corresponding to an array of CLBs on an FPGA. In essence, this embodiment allows a SIM to reserve routing resources on a target device (e.g., an FPGA), and allocate these resources to its child SIMs. Using a defined protocol, each child SIM can request and reserve routing resources, as well as placement resources (such as flip-flops and function generators in the CLBs) through the parent SIM. The routing resources are not necessarily limited to local or nearest neighbor routing.

Abstract: The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM references or includes one or more floorplanners each of which may employ one or more placement algorithms. Such placement algorithms might include, for example: a linear ordering algorithm that places datapath logic bitwise in a regular linear pattern; a rectangular mesh algorithm that implements memory in a grid pattern in distributed RAM; a columnar algorithm for counters and other arithmetic logic; or a simulated annealing algorithm for random logic such as control logic. Therefore, a design including more than one SIM can utilize a plurality of placement algorithms at the same or different levels of hierarchy.

Abstract: The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters that may, for example, include the required timing, data width, number of taps for a FIR filter, and so forth. In one embodiment, the SIM parameters may be symbolic expressions, which may comprise strings or string expressions, logical (Boolean) expressions, or a combination of these data types. The variables in these expressions are either parameters of the SIM or parameters of the “parent” of the SIM. Parametric expressions are parsed and evaluated at the time the SIM is elaborated; i.e., at run-time, usually when the design is mapped, placed, and routed in a specific FPGA.

Abstract: A plurality of flash electrically erasable programmable read only memory (EEPROM) cells is disclosed wherein metal lines couple both the sources and the drains of the flash cells. Reading of these flash cells is accomplished by applying a positive voltage to the source and reading from the associated metal source line. A soft erase scheme for increasing the threshold voltage of over-programmed flash cells is provided that prevents the leakage caused by applying a positive voltage to the drain.

Abstract: An interactive graphical software tool is provided that can be used to report the configuration data (i.e., the state of the various configuration bits) in a programmed device as well as to probe and stimulate circuits in the programmed device. A graphical or textual representation of the configuration data can be displayed. When used with a programmable device having addressable flip-flops, such as a member of the Xilinx XC6200 family, one embodiment of the invention can change the state of any addressable flip-flop in the configured device. The graphical tool of the invention is preferably implemented using a high level programming language such as Java and features a graphical point and click user interface, remote access to hardware, and symbolic debug capability.

Abstract: A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.