Abstract: The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM references or includes one or more floorplanners each of which may employ one or more placement algorithms. Such placement algorithms might include, for example: a linear ordering algorithm that places datapath logic bitwise in a regular linear pattern; a rectangular mesh algorithm that implements memory in a grid pattern in distributed RAM; a columnar algorithm for counters and other arithmetic logic; or a simulated annealing algorithm for random logic such as control logic. Therefore, a design including more than one SIM can utilize a plurality of placement algorithms at the same or different levels of hierarchy.

Abstract: The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters that may, for example, include the required timing, data width, number of taps for a FIR filter, and so forth. In one embodiment, the SIM parameters may be symbolic expressions, which may comprise strings or string expressions, logical (Boolean) expressions, or a combination of these data types. The variables in these expressions are either parameters of the SIM or parameters of the “parent” of the SIM. Parametric expressions are parsed and evaluated at the time the SIM is elaborated; i.e., at run-time, usually when the design is mapped, placed, and routed in a specific FPGA.

Abstract: An interactive graphical software tool is provided that can be used to report the configuration data (i.e., the state of the various configuration bits) in a programmed device as well as to probe and stimulate circuits in the programmed device. A graphical or textual representation of the configuration data can be displayed. When used with a programmable device having addressable flip-flops, such as a member of the Xilinx XC6200 family, one embodiment of the invention can change the state of any addressable flip-flop in the configured device. The graphical tool of the invention is preferably implemented using a high level programming language such as Java and features a graphical point and click user interface, remote access to hardware, and symbolic debug capability.