Patents Represented by Attorney Jurgen K. Vollrath
  • Patent number: 8004303
    Abstract: In a MEMS wafer, film stresses are measured by placing an inductor array over or under the wafer and measuring inductance variations across the array to obtain a map defining the amount of bowing of the wafer.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: August 23, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Peter J. Hopper
  • Patent number: 7973386
    Abstract: In a bipolar device an intrinsic Zener like diode is formed for controlling the triggering voltage and leakage current, the Zener-like diode being formed between the n-collector and the p-base, wherein the collector implant and base diffusion overlap at least partially.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: July 5, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Vladimir Kuznetsov, Peter J. Hopper
  • Patent number: 7968913
    Abstract: In an AlGaN channel transistor formed on a <100> orientation silicon wafer, a hole with walls slanted at 54 degrees is etched into the silicon to provide a <111> orientation substrate surface for forming the AlGaN channel transistor.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: June 28, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French
  • Patent number: 7910951
    Abstract: In a CMOS implemented free or parasitic pnp transistor, triggering is controlled by introducing a low side zener reference voltage.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: March 22, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Vladislav Vashchenko
  • Patent number: 7714355
    Abstract: In a BSCR or BJT ESD clamp, the breakdown voltage and DC voltage tolerance are controlled by controlling the size of the collector of the BJT device by masking part of the collector.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: May 11, 2010
    Assignee: National Semiconductor Corp
    Inventors: Vladislav Vashchenko, Alexei Sadovnikov, Peter J. Hopper, Andy Strachan
  • Patent number: 7705403
    Abstract: In a LVTSCR or snapback NMOS ESD structure, low voltage protection as well as higher voltage protection is provided by introducing a floating gate that capacitively couples with the control gate of the ESD structure and programming the floating gate to have different charges on it as desired.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: April 27, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Yuri Mirgorodski, Peter J. Hopper
  • Patent number: 7639464
    Abstract: In a dual direction ESD protection structure, first and second NMOS devices are serially connected back-to-back by connecting their drains or their sources using a common floating interconnect, while ensuring that the devices remain isolated from each other.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: December 29, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • Patent number: 7635614
    Abstract: An NLDMOS SCR device based on an LDMOS fabrication process includes a dual gate to provide controllable switching characteristics to allow it to be used for ESD protection of fast switching voltage regulators.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: December 22, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Vladimir Kuznetsov, Vladislav Vashchenko, Peter J. Hopper