Abstract: A chemical mixture of liquid crystal and a substance that lowers the clear/opaque transition temperature of the liquid crystal, thins the liquid crystal, and makes the liquid crystal more sensitive to heat generated in the lower layers of an integrated circuit chip during IC hot spot testing. The substance can be a solvent or a diluent comprising a ketone or an alcohol.

Abstract: A differential amplifier amplifies input signals and includes first and second differential input transistor pairs. The first input pair controls output voltages by adjusting sink currents coupled to the outputs. The second pair of transistors compliments the first pair by dynamically adjusting a current sourced to the outputs. A common mode circuit has also been described that adjusts both the current sourced to the outputs and the sink currents. In one embodiment, the amplifier is fully differential and controls both current source transistors and current sink transistors coupled to the amplifiers outputs.

Abstract: A method and apparatus for developing placement characteristics of a circuit design in conjunction with developing functional aspects of the circuit. In various embodiments, an application programming interface (API) is programmed in a hardware definition language (HDL). The API provides placement directives that can be called from the HDL code that defines functional characteristics of the circuit. The API can also be used in a testbench in order to analyze both the functional and physical placement characteristics of the design. Since the API is programmed in HDL, the placement generated during the implementation phase is the same as the placement analyzed during functional simulation.

Abstract: A method and apparatus for placement into a programmable gate array of I/O design objects having different I/O attributes. The I/O attributes of an I/O design object define the electrical characteristics of the design object. The programmable gate array has a plurality of sites (IOBs) arranged into banks supporting a variety of electrical interface characteristics. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between I/O attributes of I/O design objects as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, sets of I/O attributes are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.

Abstract: A CPLD employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.

Abstract: The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of a positive charge pump is begun after the charging of a negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from the negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected. Thus, the comparator generates a trigger signal when the voltage at the node decreases to the second reference voltage.

Abstract: A high-speed, low distortion line driver that includes an amplifying circuit and a differential input amplifier. The differential input amplifier includes a 1st amplifying transistor, a 2nd amplifying transistor, a 1st controlled current source, and a 2nd controlled current source. The 1st amplifying transistor is coupled in series with the 1st controlled current source and the 2nd amplifying transistor is coupled in series with the 2nd controlled current source. The 1st and 2nd amplifying transistors are operably coupled to receive a differential input signal and provide a gained and level shifted representation of the differential input signal based on the controlled currents provided by the 1st and 2nd current sources. The amount of gain is based on the transconductance properties of the 1st and 2nd amplifying transistors and of the 1st and 2nd current sources.