Abstract: An arrangement for switching broadband ISDN (B-ISDN) packets is disclosed. The arrangement comprises a broadband packet switch connected to B-ISDN customers and to a narrowband switch via an interface unit. B-ISDN control packets are connected by the broadband packet switch to the narrowband switch which transmits them to a control unit. The control unit responds to control messages by controlling the broadband packet switch to selectively interconnect B-ISDN customers and by controlling the broadband packet switch, the interface means and the narrowband switch to selectively interconnect B-ISDN and narrowband customers.

Abstract: A packet switching arrangement for receiving packets including broadcast addresses and connecting representations of the received packets to any combination of output ports specified in the address is disclosed. The packet routing units of the network both generate packet representations and selectively connect the representations to downstream routing units or network outputs. Packets for use with the network comprise an address portion encoded in a broadcast format or in a shorter point-to-point format and an address type character identifying the type of address in the address portion. The nodes of the network respond to the address type character of a received packet by selecting the appropriate decoding format for the packet address portion. A packet select unit decodes the address portion in accordance with the selected decoding format and selectively connects the packet to the network outputs.

Abstract: A number of communication units are connected to a time-multiplexed switch via communication links. Control messages are conveyed among the communication units and a central control whereby paths are established through the time-multiplexed switch from originating communication units to terminating communication units. One of the control messages conveyed to a terminating communication unit during call setup includes a link identifier defining the communication link between the originating communication unit and the time-multiplexed switch. In accordance with the present invention, when the originating communication unit begins transmitting data words, one bit position of each data word is used to transmit consecutive bits of the link identifier so that the link identifier is transmitted repetitively every fixed number of frames.

Abstract: A floating battery feed circuit comprising a switching-mode, flyback power converter wherein a capacitor connected to a converter transformer winding develops a relatively low voltage used to energize the converter control circuitry. The converter control circuitry prevents the operation of the battery feed circuit unless the voltage developed by the capacitor is above a predetermined magnitude. The power converter advantageously operates in only a constant-power mode regardless of loop impedance.

Abstract: A time division switching system having distributed control processors is disclosed. The distributed processors exchange control messages and cooperate in the completion of talking paths between subscribers. Each control message includes an address portion defining the destination for the control message and is transmitted to a time-shared space division switch on the same time multiplex lines that speech representations are transmitted. Control messages are routed by the time-shared space division switch to a control distribution unit where the address portion is interpreted. When the address portion defines a distributed processor which controls the time-shared space division switch, the control distribution unit transmits the associated control message directly to that processor. Alternatively, when the address portion defines one of the other distributed processors the control distribution unit transmits the associated control message to the defined processor via the time-shared space division switch.

Abstract: A control information communication arrangement for a time division switching system having distributed control processors. An originating processor transmits circuit setup request control words including an address defining a destination processor, to a control word switch via control time slots through a time-multiplexed switch. The control word switch responds by establishing a communication path to the destination processor via the time-multiplexed switch and then transmitting a status signal to the orginating processor indicating that the path has been established. In response to the status signal, the originating processor begins transmitting the control message control words which comprise a control message. Advantageously, the control word switch does not store entire control messages before conveying them to destination processors.

Abstract: A time division switching system having distributed control processors is disclosed. The switching system includes time-slot interchange units having associated subscriber sets and conference circuits and a time-shared space division network for interconnecting the time-slot interchange units. Each of the time-slot interchange units and the time-shared space division network are controlled by separate control processors. In response to called subscriber set identifying information from a calling subscriber set, the control processor associated with the time-shared space division network completes standard communication paths through the time-shared space division network to connect the time-slot interchange units associated with the calling and called subscriber set.

Abstract: An arrangement to compensate for the leakage and biasing characteristics associated with the semiconductor crosspoints of a concentrator to allow accurate telephone subscriber loop measurements to be made through the concentrator. A compensation current is supplied which varies linearly with the applied test voltage according to a relationship that is determined adaptively just prior to the test so that the effects of device differences and temperature variations are minimized. The approach is extended to nonlinear compensation.

Abstract: A dual tone multifrequency and dial pulse receiver that receives 8000 digital data words per second, each of the data words including eight PCM bits representing the analog signal transmitted from a subscriber set and also including a line status bit indicating the DC status of the line. The receiver includes a time-shared processor which processes the PCM bits of 4000 words per second to detect tone-pairs and which also processes the line status bit of 4000 words per second to detect valid dial pulse sequences. The time-shared processor stores one of a first plurality of code words in a register when a tone-pair is detected and stores one of a second plurality of code words in the register when a valid dial pulse sequence is detected. Advantageously, the receiver can detect either dual tone multifrequency or dial pulse signaling from a subscriber even though the type of signaling to be used by the subscriber is not known a priori.

Abstract: A loop communication system, interconnecting a number of nodes around the loop, in which two oppositely directed unidirectional loops service the two directions of transmission. Each of the loops comprises a time division multiplexed transmission facility. Each of the nodes has facilities for connecting the communications on each incoming channel to a utilization device connected to that node, for connecting the communication from a utilization device connected to that node to each outgoing channel, or for repeating the communication from any incoming channel to a corresponding outgoing channel. Assignment of a communication to a given channel is accomplished using a centralized control means which causes the communicating devices to be connected using corresponding channels in the two loops, and using that portion of the loop which has the smaller number of intermediate nodes.

Abstract: A fault and error detection arrangement for detecting transmission and routing errors made by systems in which a central data transmitter/receiver (601, 610) bidirectionally intercommunicates with peripheral circuits (620) through an interconnection arrangement (604). The parity bits of certain data words transmitted by the central data transmitter (601) are intentionally inverted by a central parity inverter (602), in a known sequence. Data words transmitted by the central data transmitter (601) are routed by the interconnection arrangement (604) to the peripheral circuits (620) where parity is checked by a peripheral parity checker (621) and a parity invert signal is generated when an inverted parity data word is found. A peripheral parity inverter (623) included in each peripheral circuit (620) responds to the parity invert signals by inverting the parity bit of the next data word transmitted by a peripheral data transmitter (622) also included in each peripheral circuit (620).

Abstract: A voltage detector circuit for detecting a DC voltage on a line in the presence of a substantially fixed frequency AC voltage. The circuit may be used to detect call originations on a telephone line having longitudinal AC voltages induced thereon. The circuit compares the instantaneous voltage on the line with a reference level and repetitively increments a counter when the instantaneous voltage exceeds the reference level and repetitively decrements the counter when the instantaneous voltage does not exceed the reference level. After operating the counter for a time interval substantially equal to the period of the fixed frequency AC voltage, the most significant bit of the counter will indicate whether the DC voltage on the line is above the reference level. The circuit may also be used to detect call terminations on the line.

Abstract: An arrangement for performing subscriber loop testing through a concentrator/expandor employing semiconductor crosspoints. The crosspoints of the concentrator/expandor are relatively nonlinear when conducting currents less than a predetermined current and are relatively linear when conducting currents in excess of the predetermined current. When tests are to be applied to a given subscriber loop which comprises a tip conductor and a ring conductor, two paths are completed through the concentrator/expandor to the tip conductor and two paths are completed through the concentrator/expandor to the ring conductor. A linearizing source then transmits a current in excess of the predetermined current around the circuits formed by the two concentrator/expandor paths to each subscriber loop conductor. Test signals are then applied to the subscriber loop by connecting such signals between the two paths to the subscriber ring conductor and the two paths to the subscriber tip conductor.

Abstract: A floating, constant power, battery feed circuit wherein a single transformer is used to perform the functions of battery feed and audio coupling. AC feedback is used to control the dynamic output impedance of the circuit. To achieve a constant dynamic output impedance, the amount of AC feedback is controlled by the DC output voltage, which in turn depends on the loop resistance. To achieve a constant audio gain from the switching network to the subscriber set, the audio signal from the switching network is multiplied by a signal representing the DC output voltage.

Abstract: An arrangement and method for interconnecting the stages of a space division switching network which provides simple and continuous growth from a small number of lines to the system's maximum number of lines. The switching network comprises up to M input stage switches, center stage switches and up to M output stage switches. Incoming lines are connected to the input terminals of the input stage switches such that no input stage switch is connected to a number of incoming lines which exceeds the number of incoming lines connected to any other input stage switch by more than one. The number of center stage switches is established from a predetermined interconnection plan and at any given time, the number of center stage switches is a function of the number of lines connected to the input stage switch having the largest number of lines connected thereto. As each line is connected to an input stage switch, the output terminals of that switch are distributed over the available center stage switches.

Abstract: A time division switching system which includes a central control, two time-multiplexed switching units each having a control distribution unit associated therewith and a plurality of interface modules each including a selected active control unit. Data words representing subscriber-generated information are conveyed between interface modules by a selected one of the time-multiplexed switching units designated as active. The active time-multiplexed switching unit also conveys control messages between each of the interface modules and the control distribution unit associated with the active time-multiplexed switching unit. However, the time-multiplexed switching unit designated as standby is also used to convey control messages between each of the interface modules and its associated control distribution unit. Each of the control distribution units routes received control messages to the interface modules via its associated time-multiplexed switching unit or to the central control.

Abstract: A time division switching system having distributed control processors is disclosed. The distributed processors exchange control messages and cooperate in the completion of talking paths between subscribers. Each control message includes an address portion defining the destination for the control message and is transmitted to a time-shared space division switch on the same time multiplex lines that speech representations are transmitted. Control messages are routed by the time-shared space division switch to a control distribution unit where the address portion is interpreted. When the address portion defines a distributed processor which controls the time-shared space division switch, the control distribution unit transmits the associated control message directly to that processor. Alternatively, when the address portion defines one of the other distributed processors the control distribution unit transmits the associated control message to the defined processor via the time-shared space division switch.

Abstract: A program controlled data processing system which includes two data manipulation units generally operated in parallel. The two data manipulation units, however, by design react differently in the execution of certain program order words. The system includes a circuit arrangement which compares data generated by the two data manipulation units and generates comparison signals indicating the identity or lack of identity of the compared data. The comparison signals are utilized in the detection of faults and errors and in the determination of conditions as defined by the program.