Abstract: A VDMOS device includes a wafer of semiconductor material having first and second opposed major surfaces. A drain region of a first conductivity type extends along the one major surface. A plurality of body regions of a second conductivity type is in the body region at the one major surface. Each body region forms with the drain region a body/drain PN junction, the intersection of which with the first major surface is in a closed path, preferably a hexagon. A plurality of spaced source regions of the one conductivity type are in each of the body regions with each source region being positioned opposite the space between two source regions in the adjacent body region. Each source region forms with the body region a source/body PN junction. A portion of each of the source/body PN junctions is adjacent to but spaced from its respective drain/body PN junction to form a channel region therebetween. An insulated gate is over the first major surface and the channel regions.

Abstract: SOI islands having doped edges are formed by providing over the surface of a layer of single crystalline silicon on an insulating substrate a masking layer formed of two layers, the lowermost layer adjacent the silicon layer being silicon oxide and the uppermost layer being silicon nitride. The masking layer is defined using standard photolithographic techniques and etching to form the masking layer over only the areas of the silicon layer which are to form the islands. The uncovered portion of the silicon layer is then removed by etching to form the islands. The lowermost layer of the masking layer is then etched laterally away from the edges of the island to expose a portion of the surface of the silicon layer adjacent the edges of the islands. After removing the uppermost layer of the masking layer, the exposed edge portions of the surface of the silicon layer are doped by ion implantation to form the islands with doped edges.

Abstract: A packaging assembly for electrical components includes a heat sink having a mounting surface upon which certain ones of the electrical components are mounted. An associated lead frame is rigidly secured to an edge of the heat sink, and one or more extended ends of selected leads thereof are formed into mounting pads positioned over the mounting surface of the heat sink for receiving other ones of the electrical components. Dielectric material is positioned between the mounting pads and the heat sink, for electrically isolating the electrical components mounted upon the mounting pads from one another and from electrical components mounted directly on the heat sink. The electrical components and proximate ends of the leads of the lead frame are electrically interconnected via electrical conductors, and the assembly is encapsulated with a plastic material about the heat sink and proximate ends of the lead frame, whereafter bridge elements between the leads of the lead frame are severed.

Abstract: An hermetically sealed package for a die comprised of a base plate, a side wall mounted on the brace plate, a printed circuit board connecting terminals on one side of the die to a first lead, connector clips connecting terminals on the other side of die to a bus having posts extending, wires connecting other terminals on the other side of the die to runners on the circuit board, leads respectively extending from each runner, a cover lid hermetically sealed to the side wall, the lid having openings hermetically sealed by insulators having slots through which the leads respectively extend in sealed relationship.

Abstract: The present invention relates to a power MOS transistor having a current limiting circuit incorporated in the same substrate as the transistor. The power MOS transistor includes a drain region extending through the substrate between opposed first and second surfaces, a plurality of body regions in the substrate at the first surface, a separate source region in the substrate at the first surface within each body region and a channel extending across each body region between its junction with its respective source region and its junction with the drain region. A conductive gate is over and insulated from the first surface and extends over the channel regions. A first conductive electrode extends over and is insulated from the gate and contacts a first portion of the source regions. A second conductive electrode extends over and is insulated from the gate and contacts a second portion of the source regions. The second portion contains a smaller number of the source regions than the first portion.

Abstract: By comparing the distorted image of an edge pattern, such as a checker board pattern, reflected from the surface of a work piece, such as a silicon wafer, and received by a solid state television camera, with a similar image, reflected from the optically flat surface of a calibration piece substituted for the work piece, surface height irregularities, such as warpage, of the work piece can be measured with a high sensitivity and a large dynamic range at relatively low cost.

Abstract: A dimension of an object disposed on a substrate, such as the width of a line of material deposited on a substrate in an integrated circuit manufacturing procedure, is measured by directing a plane wave of electromagnetic energy of predetermined dimensions toward the object at a predetermined angle of incidence. Electromagnetic energy scattered from two predetermined parts or features, such as the edges, of the object are combined so that they produce an interference pattern in space varying between maxima and minima. The characteristics of the interference pattern permit the dimension of the object to be deduced.

Abstract: A CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity type having an isolation region of an insulating material extending into the body from the major surface along the junction of the well regions. Thin layers of silicon oxide are formed on the major surface over each of the well regions, and a gate line of conductive polycrystalline silicon is formed over each of the silicon oxide layers. The side walls of the gate lines are covered with a layer of silicon oxide. A layer of polycrystalline silicon is selectively deposited on the surface of the body at each side of each gate line and on the gate lines. A layer of a refractory metal is deposited on the polycrystalline silicon layer. The polycrystalline silicon layer is heated to cause the metal to react with the silicon and form a metal silicide region at least partially through the polycrystalline silicon layer.

Abstract: A method for using a self-aligned metallic mask for formation of a shallow source/drain, lightly doped drain metal-oxide-semiconductor device having a self-aligned low-resistivity silicide/polysilicon gate for greater device speed. The invention involves coating a semiconductor wafer in an intermediate stage of processing with a refractory metal layer over a polysilicon layer. The refractory metal layer is patterned and etched to expose corresponding portions of the underlying polysilicon layer, and then the wafer is preamorphized. After appropriate doping of N+ and P+ regions, the semiconductor wafer is subjected to an annealing process, which sinters the metal layer with the underlying polysilicon layer to form a silicide. The silicide provides a low resistivity path for the transistor structures, resulting in greater device speed. Use of the self-aligned metallic mask permits the fabrication of lightly doped drain semiconductor devices having shallow source and drain regions.

Abstract: A method of making a MOS transistor having source and drain extensions includes forming on a surface of a substrate of single crystalline silicon a gate line having a thin layer of silicon oxide between the gate line and the substrate surface. A light dose of ions of a desired conductivity type are embedded in the substrate surface at each side of the gate line up to the side walls of the gate line. Spacers of thermally grown silicon oxide are formed on the side walls of the gate line and a dose of the ions of the desired conductivity type are embedded into the substrate surface at each side of the gate line to form source and drain regions. The source and drain regions extend up to the spacers and have lightly doped extensions extending up to the side walls of the gate line under the spacers.

Abstract: A method for forming dielectrically isolated devices comprises forming a first insulating layer on a flat monocrystalline surface of a silicon wafer. A plurality of active regions is defined on the surface using existing manufacturing masks. Portions of the insulating layer not included in the device regions are removed, leaving apertures. Silicon is epitaxially deposited within the apertures and over the first insulating layer so as to form a continuous monocrystalline layer. The surface of the monocrystalline is oxidized. The resulting oxide is then removed, thereby exposing the surface of the monocrystalline layer having its thickness reduced. A second insulating layer is formed over the monocrystalline layer, and a layer of silicon nitride is deposited over the second insulating layer. The plurality of active regions is defined on the layer of silicon nitride, again using existing manufacturing masks.

Abstract: A hermetically sealed housing for a solid state device or the like includes a metal header having a mounting surface and a metal cap mounted on the header and over the mounting surface. The cap includes a cup-shaped portion and a flange extending radially outwardly from the rim of the cup-shaped portion. A weld ring projects from a surface of the flange toward the header mounting surface and is welded to the mounting surface. A second ring projects from the surface of the flange and is spaced radially inwardly from the weld ring. The second ring is shorter than the weld ring so that it preferably just contacts the mounting surface of the header. The second ring captures any metal particles splashed from the weld ring during the welding of the cap to the header and thereby minimizes particle induced noise.

Abstract: A silicon-on-insulator (SOI) semiconductor device is made by forming a layer of single crystalline silicon on the surface of an insulating substrate. Portions of the silicon layer are removed, such as by etching, to form islands of the single crystalline silicon on the substrate with the islands having sharp corners between their side walls and their top surface. The silicon islands are then exposed to vapors of hydrogen chloride which etch the corners and form the islands with smooth, rounded corners between the side walls and the top surface.

Abstract: A bipolar transistor includes a substrate of semiconductor material having an expitaxial body of the semiconductor material on a surface thereof. The semiconductor body has a major surface. A collector region of one conductivity type is in the body at the major surface and a base region of the opposite conductivity type is in the collector region at the major surface and forms with the collector region a collector/base junction which extends to the surface. A plurality of emitter regions of the one conductivity type are in the base region and form with the base region emitter/base junctions which extend to the surface. At least some of the emitter/base junctions are adjacent to but spaced from the collector/base junction at the major surface. A layer of insulating silicon oxide is on the major surface and a layer of conductive polysilicon is on the insulating layer.

Abstract: An isolation structure for isolating a pilot device from the main device of a monolithic semiconductor device. The isolation structure comprises a pair of spaced isolation channels separating the pilot device from the main device. An electrode insulatively disposed over the region between the two isolation channels is shorted by a metallization layer to the isolation channel closest to the pilot device. In this manner, parasitic transistor turn on of the isolation structure is prevented.

Abstract: A SOI integrated circuit includes a plurality of islands of single crystalline silicon on a surface of a substrate of an insulating material. Each of the silicon islands contains an electrical component, such as a MOS transistor. A layer of silicon oxide is on the surface of the substrate between the islands and is slightly spaced, at least about 0.1 micrometers, from each of the silicon islands. A line of a conductive material, such as conductive polycrystalline silicon, extends over the silicon islands and between the silicon islands over the silicon oxide layer. The silicon oxide layer isolates the conductive line from the substrate so that any photocurrent generated in the substrate as a result of the integrated circuit being exposed to radiation will not flow through the conductive line to disrupt the circuit.

Abstract: The present invention relates to a method of forming gate lines of polycrystalline silicon, polysilicon, which may have a layer of a metal silicide thereon. The gate lines are formed over islands of silicon on an insulating substrate with the islands being covered with a layer of silicon oxide. A polysilicon layer is coated over the silicon oxide layer on the silicon island and on the adjacent surface of the substrate. Resist masking strips are formed over the area of the polysilicon layer which are to form the gate lines. The exposed area of the polysilicon layer is first plasma etched in a gaseous mixture of nitrogen, chlorine and chloroform. The chlorine etches the polysilicon and the chloroform forms a protective coating of a polymer over the side walls of the formed gate lines. The device is then subjected to a second plasma etch in a gaseous mixture of helium, chlorine and carbon dioxide.

Abstract: A semiconductor device, such as a MOSFET or IGT, with a deep base region having a high dopant concentration at least as high as 5.times.10.sup.19 atoms per cubic centimeter and a method of fabrication are disclosed. The novel method involves formation of the deep base region at a later stage in the fabrication and reduces the leaching of dopant from the deep base region, as well as achieving greater control over the dopant concentration in the deep base region. Further, the increased dopant concentration in the deep base region lowers the base shunt resistance of the device to provide improved electrical ruggedness. For IGTs, parasitic thyristor action is reduced.

Abstract: For fine line lithography of a reflective substrate, a layer of titanium nitride is applied between the reflective surface and the photoresist that is absorbant at the wavelength of light used to expose the photoresist. The resolution of the photoresist is improved, even when an absorbant dye is used in the photoresist. The titanium nitride can be readily removed at the same time as the reflective layer is patterned, thereby avoiding the need of a separate step to remove the absober layer during etching of the reflective substrate.

Abstract: An insulated gate device includes at least one cell having base and emitter region surfaces disposed in ohmic contact with a metallic emitter electrode. The cell is constructed to provide a larger ratio of base region surface area to emitter region surface area in contact with the emitter electrode than is found in the prior art. The cell is further constructed to provide paths for reverse current flow from a drift region through the base region and to the emitter electrode; these paths being spaced form the cell's emitter-base junction.