Abstract: An improved I/O interrupt sequencing method and apparatus including generation of an instruction priority request signal to indicate that a real time task requires programmed I/O service. Generating an end of chain signal to suspend burst I/O control of the I/O bus and allow programmed I/O service to a real time device, and resetting the instruction priority request signal to allow burst mode data transfer to continue at the count positions at which it was suspended.

Abstract: Described is an interactive enquiry system in which a complete data base is contained at a host computer. Local terminal sub-systems are remotely connected to the host with each local sub-system containing a local data base. Each local data base is dynamically maintained so that the most frequently used pages are retained in local storage. If storage space needs to be created, the least frequently used pages are discarded from the local data base.

Abstract: This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two bit decoder for receiving each like order pairs of digits A.sub.i, B.sub.i of two n digit binary numbers A.sub.0, A.sub.1....A.sub.n-1 and B.sub.0, B.sub.1....B.sub.n-1 plus a carry C.sub.in. The decoders generate an output signal called a min term on a different line for each of the four possible combinations A.sub.i B.sub.i, A.sub.i B.sub.i, A.sub.i B.sub.i and A.sub.i B.sub.i of the true and complement of each pair. The min terms from the decoders are fed to an array called the product term generator or AND array which generates product termsf.sub.p =f.sub.0 (A.sub.0,B.sub.0) f.sub.1 (A.sub.1,B.sub.1)....f.sub.n-1 (A.sub.n-1, B.sub.n-1) f.sub.n (C.sub.in)The product terms are fed to a second array called a sum of product term generator or OR array that sums product terms f.sub.p.

Abstract: An improved logical OR circuit is shown wherein the load resistance is divided into drain resistance and source resistance, each resistance having a lower value than could be employed with a single load resistance while at the same time keeping power dissipation to low levels. The use of relatively lower resistances permits faster voltage rise time, thereby permitting faster programmed logic array (PLA) operation. The voltage drop across the source resistance is made small when the output device is conducting by providing a substantially higher drain resistance load for the output device with respect to the drain resistance of the input devices.

Abstract: An improved method for verifying the identity of a prospective terminal user presenting an identification card or a credit card and a memorized personal identification number. Only part of the information necessary to correlate an account number to a personal identification number is available at any accessible place in the operating system. Neither the credit card, the host computer, nor the transmission link will ever have sufficient information to completely correlate an account number to a personal identification number.

Abstract: This specification describes arrays for performing logic functions. In these arrays input variables are placed on a series of parallel input lines that intersect a number of parallel output lines in a grid of intersections. Field effect devices at these intersections have their gate terminals connected to one of the input lines and their source terminal connected to one of the output lines and through a load device to a source of potential. The drain terminals of these devices are either unconnected, connected directly to ground or connected to ground through one of two switching devices. The devices with unconnected drains are inoperative. The devices with their drains connected directly to ground are operative at all times. While the devices connected to ground through one of the switches are operative only when the switch is closed. The array can be time shared by two different logic functions by having one or the other of the switches off at any given time.

Abstract: A method and a device for modifying a stream of information elements, particularly with a view to compensating for variations of the speed at which such elements are transmitted over the successive portions, or links, of a transmission network.

Abstract: A simplified loop communication fault location and isolation circuit which utilizes sequences of power interruption pulses in DC power distributed on the signal lines from a master repeater to control loop signal wrap functions.

Abstract: A processor including a plurality of synchronized subprocessors, each implemented on an integrated circuit substrate and each having an instruction register and instruction executing circuits for independently executing a portion of the functions required by an instruction being simultaneously executed by each subprocessor. Execution is initiated and synchronized by simultaneously loading the same instruction into each subprocessor.

Abstract: Dynamic logic counting circuits are disclosed using recirculating latched memory stages having parallel shift circuits operating in synchronism with the latch circuits to control stepping of the counts. An alternate embodiment employs steering circuit controlled subcounters, each subcounter having a parallel shift circuit operating in synchronism with its respective subcounter to step the next succeeding subcounter when its respective subcounter reaches a predetermined count such as 9 for a binary coded decimal counter or 15 for a binary counter.